Spartan-6

All packages are ASCII files in txt format.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

This guide describes the clocking resources available in all Spartan®-6 FPGAs, including the DCMs and PLLs.

This guide describes the Spartan®-6 FPGA block RAM capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

This user guide provides information on the various hardware methods of power management in Spartan®-6 FPGAs, primarily focusing on the suspend mode.

The Spartan®-6 FPGA GTP Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx provides a simulation environment for evaluating channel designs for Spartan-6 FPGA GTP transceivers. This document describes how to install the SIS kit and get started with simulations.

EN113: Errata for Spartan®-6 LX16 CES FPGAs.

EN115: Errata for Spartan®-6 LX150 CES FPGAs.

EN117: Errata for Spartan®-6 LX45 CES FPGAs.

EN118: Errata for Spartan®-6 LX45T CES FPGAs.

EN124: Errata for Spartan®-6 LX150T CES FPGAs.

EN146: Errata for the Spartan®-6 FPGA LX4, LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9953 devices.

EN147: Errata for the Spartan®-6 FPGA LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9951 devices.

EN148: Errata for the Spartan®-6 FPGA production devices.

EN168: Errata for the Lower Power Spartan®-6 FPGA LX production devices.

This Answer Record describes the Known Issues for the Spartan-6 FPGA family used with ISE Design Suite 13. 

The purpose of this notification is to inform Xilinx customers of a change to the Memory Controller Block (MCB) performance, an update to the JTAG ID Revision Code, a change to the maximum ICCINTQ and ICCAUXQ specifications, and an update to the CSG324 Bank 0/2 SSO limit recommendations for “XC” Commercial Spartan®-6 LX16 -2C and Spartan-6 LX45 -2C FPGA production devices.

To communicate a mask change for all production Spartan®-6 FPGA devices and a speed file change for all Spartan-6 –3N speed devices.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan®-6 FPGA Phase Locked Loop (PLL) through its Dynamic Reconfiguration Port (DRP).

设计文件:

• xapp879.zip

This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.

设计文件:

• xapp492_S6_ConnectivityTRD_Aurora.zip

This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed spread-spectrum generation without any logic or in a soft spread-spectrum solution using a state machine.

设计文件:

• xapp1065.zip

This application note discusses how to efficiently use the Spartan®-6 FPGA ISERDES and OSERDES primitives in conjunction with the input delay blocks and phase-detector circuitry.

设计文件:

• xapp1064.zip

100% Material Declaration Data Sheet CPG196 for Spartan®-6 FPGAs

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet: CSG324

设计文件:

• IPC-1752 Form

Package Drawing.

100% Material Declaration Data Sheet FTG256 Package for Spartan-6 FPGAs

设计文件:

• IPC-1752 Form

196 Ball Chip-Scale BGA (CPG196) Package

Material Declaration Data Sheet, FG676 Package for Spartan-6 FPGAs

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet FGG484

设计文件:

• Material Composition Declaration, FGG484 (IPC-1752 Format)

设计文件:

• Material Composition Declaration, CSG225 (IPC-1752 Format)

Package drawing.

设计文件:

• IPC-1752 Form

设计文件:

• IPC-1752 Form

设计文件:

• IPC-1752 Form

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet, FGG676 Package for Spartan-6 FPGAs.

设计文件:

• IPC-1752 Form

This characterization report compares the electrical performance of the Spartan®-6 FPGA GTP transceiver against the PCI Express® Revision 1.1 specifications published in the PCI Express Base Specification, Revision 1.1 and the PCI Express Card Electromechanical Specification, Revision 1.1. All testing for this report is based on a line rate of 2.5 Gb/s across voltage, temperature, and worst-case transceiver performance corners.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

This white paper discusses targeting guidelines and other considerations needed to achieve optimal designs with Spartan®-6 devices.

This white paper discusses how synthesis and implementation can help to optimize the performance of Spartan®-6 designs.

This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

This white paper discusses the observed performance of the Spartan®-6 FPGA Connectivity targeted reference design. The design uses PCI Express®, Ethernet, and an integrated memory controller along with a packet DMA for moving data between system memory and the FPGA.

ISE® Design Suite v12 is the production-optimized tool suite for Virtex®-6 and Spartan®-6 FPGAs that delivers innovation in three critical areas of FPGA design: power reduction, productivity, and performance.

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.

This white paper describes how design engineers can take advantage of Virtex®-6, Spartan®-6, and 7 series FPGAs to handle the complexity of designing portable ultrasound systems and bring cutting-edge ultrasound technology to market quickly within cost and power constraints.

The AXI4 specification represents a major evolutionary step in interconnect technology for on-chip system design. The value of the AXI4 interconnect has many facets, beginning with an immediate gain in productivity derived from a unified IP interconnect standard that supplants legacy and custom interconnect architectures. The three interconnect protocols developed for the AXI4 standard (AXI4, AXI4-Lite, and AXI4-Stream interfaces) provide the flexibility to optimize an FPGA design for performance, throughput, latency, or area.

The purpose of this white paper is to describe how Spartan®-6 FPGAs address the needs of high-volume systems. The ability to connect efficiently and inexpensively to commodity memories, high-performance chip-to-chip interface capability, and innovative power down modes are just a few of the problems solved by high-performance, low-power, and low-cost Spartan-6 FPGAs.