Device User Guides

This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

This guide describes the Spartan®-6 FPGA block RAM capabilities.

This guide describes the Virtex®-5 FPGA RocketIO™ Transceiver Signal Integrity Simulation (SIS) Kit for Synopsys HSPICE.

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This guide describes the Embedded Tri-Mode Ethernet Media Access Controller (MAC) available in the Virtex®-4 FX family.

This guide describes the GTH transceivers available in all Virtex®-6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package.

The Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation Kit for Synopsys HSPICE enables signal integrity simulations of a communication link between Virtex-6 FPGA GTX transceivers. This kit includes models of the line driver of the transmitter and the analog front end of the receiver of the GTX transceivers.

This guide describes the System Monitor functionality available in all Virtex®-5 devices.

This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

本技术文档中描述的参考设计，可用作Xilinx嵌入式解决方案的介绍，特别是PowerPC™处理器。 它也包含了Xilinx Platform Studio™工具和内含的Base System Builder™向导。 最后，本参考设计阐明了如何为PowerPC APU接口添加定制或第三方IP。

本技术文档讨论了时序模型、设计考虑因素、配置、PCB 设计考虑因素、BitGen 和 PROMGen 的 Switches 和 Options，以及 PROM 信息。

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

This guide provides information about how to use the Video Starter Kit (VSK) to begin experimenting with video processing using the Spartan®-3A DSP family of FPGAs.

This User Guide describes the Xilinx Power Estimator (XPE), a power estimation tool used in the predesign and preimplementation phases of a design to be implemented in a Xilinx FPGA. XPE works with Microsoft Excel.

This advance specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

本指南描述了 XtremeDSP™ slice，文档包括使用 DSP48 数学函数和各种 FIR 滤波器的参考设计。

本用户指南对收发器提供了概述，以及数字设计考虑因素、模拟设计考虑因素、仿真和实现选项、时序模型、有效数据/控制字符和 RocketIO 相关的在线出版物。

The Virtex®-4 FPGA User Guide includes chapters on Clocking Resources, Digital Clock Manager (DCM), Phase-Matched Clock Dividers (PMCD), Block RAM and FIFO memory, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

ML32x 平台的 RocketIO BERT 参考设计演示了嵌入到单个 Virtex-II Pro FPGA 内的两个 RocketIO 千兆位级收发器 (MGT) 端口之间的 2.5 Gbps 到 3.125 Gbps 串行链路。

RocketIO™ X 收发器具有灵活的可编程特性，可以轻松地将千兆位级串行收发器 (MGT) 集成到任何 Virtex-II Pro™ X 设计中。

针对 ML42x 开发平台的 Virtex™-4 RocketIO 误码率测试器 (XBERT) 参考设计演示了嵌入到单个 Virtex-4 FPGA 中的两个或更多 Virtex-4 RocketIO 千兆位级收发器 (MGT) 端口间的串行链路。 本用户指南提供了在 ML421、ML423、ML424 和 ML425 平台上设置和运行 XBERT 参考设计的说明。

This guide describes the RocketIO™ GTX transceivers available in the Virtex®-5 TXT and FXT platform devices.

This guide describes the System Monitor functionality.

This reference guide describes the embedded processor block available in the Virtex®-5 FXT platform.

This guide describes the RocketIO™ GTP transceivers available in the Virtex®-5 LXT and SXT devices.

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

本指南介绍了 Virtex®-4 器件管脚和封装规范；它还包括管脚分配图和热特性数据。

This guide describes the Spartan®-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

Platform Flash PROM 用户指南描述了 Platform Flash PROM 系列器件的高级特性。该指南还包括配置设置、用于对该 PROM 系列进行编程的文件的生成、和其它设计考虑。

This guide explains how to install the Xilinx® family of USB programming cables, including information related to installing Xilinx USB cables with ISE® and WebPACK™ software.

针对配置完成后，需要从在系统 Flash 存储器中读出或向其中写入数据的 Spartan™-3AN FPGA 的应用。

Spartan-II™ FPGA 系列产品在数据手册和应用指南中进行了描述，但没有独立的用户指南。 该页列出了其它系列的用户指南里找到的具有同类型信息的技术文档。

本技术文档包括了关于时序模型、设计考虑因素、配置、PCB 设计考虑因素、BitGen 和 PROMGen Switches，以及 XC18V00 系列 PROM 的信息。

Spartan™-IIE FPGA在一些数据手册和应用指南里进行了介绍。它没有单独的用户指南。该页列出了具有同类信息的其它器件系列的用户指南技术文档。

This document describes the Virtex®-5 FPGA DSP48E slice.

本用户指南介绍了在 MK322 和 MK325 平台上设置和操作 RocketIO™ X BERT 参考设计。

本全方位配置指南包括配置接口（串行和 SelectMAP）、比特流加密、边界扫描与 JTAG 配置和重新配置技术方面的章节。

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

This user guide provides Virtex®-5 device pinouts, package specifications, pinout diagrams, PCB design rules, and thermal data.

本用户指南讨论了利用 Virtex™-II Pro 器件和 Virtex-II Pro 唤醒解决方案进行硬件和软件数据管理。

本技术文档介绍了各种工作条件下的 I/O 行为。它介绍了如何使用不同的终端模式，如何理解阈值，以及加载是如何影响 I/O 的。

This user guide is a detailed functional description of XtremeDSP™ Solution Spartan™-3A DSP technology.

本指南针对 Virtex-4 系列介绍了 PCB 指导。 它涵盖了 SelectIO 信号传输、RocketIO 信号传输、功率分配系统、PCB 布线和器件布局。

目的是介绍 Xilinx 推出的 Spartan™-3A DSP 入门套件的功能和内容。本技术文档对电路板操作进行了说明，并介绍了硬件特性。

Virtex™-4 RocketIO™ 千兆位级收发器用户指南为产品设计者提供了在 Virtex-4 设计中成功实现 RocketIO MGT 的详细技术信息。

本用户指南介绍了 Platform Flash XL 的特性集，并且演示了支持的常见配置模式设置。

本指南提供了采用栅距为 1.00-mm 的陶瓷倒装片圆柱栅格阵列（CF）封装的 Virtex®-4 QPro™-V（QV）抗辐射 FPGA 的完整封装信息。Virtex-4 V 抗辐射 FPGA 仅采用陶瓷倒装片圆柱栅格阵列（CF）封装，特别适于提高热循环可靠性。

This user guide provides an overview of the Xilinx Video Over IP system.

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

This contains reference systems for the Spartan®-3A DSP 3SD1800A MicroBlaze™ Reference Systems

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

This guide describes the functionality of the dedicated PCI Express Endpoint block available in the Virtex®-5 LXT, SXT, and FXT Platforms.

This guide describes the clocking resources available in all Spartan®-6 FPGAs, including the DCMs and PLLs.