Virtex-5

Errata for Virtex®-5 TXT and FXT FPGAs.

Errata for the following Virtex®-5 devices: XC5VFX30T CES, XC5VFX70T CES, XC5VFX100T CES, XC5VFX130T CES, and XC5VFX200T CES FPGAs

Errata for the following Virtex®-5 devices: XC5VFX30T, XC5VFX70T, XC5VFX100T, XC5VFX130T, and XC5VFX200T CES9988 FPGA

下列 Virtex™-5 LXT 器件：XC5VLX30TCES、XC5VLX50TCES、XC5VLX110TCES 和 XC5VLX330TCES 勘误表。

下列 Virtex®-5 SXT 器件：XC5VSX35TCES 和 XC5VSX50TCES 勘误表。

Virtex™-5 ES 器件：XC5VLX30CES、XC5VLX50CES、XC5VLX85CES、XC5VLX110CES、XC5VLX220CES 和 XC5VLX330CES 勘误表。

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Fibre Channel specifications.

本报告描述了 Virtex™-5 GTP 收发器相对于通用公共无线电接口 (CPRI) 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 PCI Express 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 OC-48 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 10 Gb 连接单元接口 (XAUI) 指标的电气性能特性描述测试。

本报告描述了 GTP 收发器相对于千兆位级以太网串行协议标准的电气特性描述测试。

This report documents the results of characterization performed on the Virtex™-5 Clock Management Tile(CMT) that combines two enhanced Digital Clock Managers (DCMs) with one Phase-Locked Loop (PLL), and clocking resources.

本特性描述报告提供了 Virtex®-5 LXT 和 SXT RocketIO™ GTP 收发器在指定工艺、电压和温度（PVT）条件下的 FPGA 特性描述结果。

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Serial ATA Generation 2 (3 Gb/s) specification.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-4 RocketIO™ MGT.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-II Pro RocketIO™ MGT.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against OIF-CEI-02.0, "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O".

This guide describes the functionality of the dedicated PCI Express Endpoint block available in the Virtex®-5 LXT, SXT, and FXT Platforms.

This guide describes the RocketIO™ GTX transceivers available in the Virtex®-5 TXT and FXT platform devices.

This guide describes the System Monitor functionality available in all Virtex®-5 devices.

This user guide provides Virtex®-5 device pinouts, package specifications, pinout diagrams, PCB design rules, and thermal data.

This document describes the Virtex®-5 FPGA DSP48E slice.

This guide describes the RocketIO™ GTP transceivers available in the Virtex®-5 LXT and SXT devices.

This reference guide describes the embedded processor block available in the Virtex®-5 FXT platform.

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller (MAC) available in Virtex®-5 devices.

This application note describes how to indirectly program select BPI PROMs through the JTAG interface of a Virtex®-5 FPGA using iMPACT. The required hardware setup, BPI-UP PROM file generation, and the indirect programming flow are described.

Previous generations of Xilinx® FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex® family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note provides an overview of the architecture and function of avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7. It also describes how to map various functional blocks required for an AFDX end system to the Virtex®-4 and Virtex-5 architectures.

本应用指南描述了在 Virtex™-5 器件中实现的 200-MHz DDR SDRAM 存储器控制器。 本参考设计使用了 Virtex-5 ChipSync 功能来校准和调整读数据时序。 DDR 提供了一个简单的后端用户接口，使其集成进完整的 FPGA 设计。

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

热插拔是指把未上电的板插到已上电（热）运行系统上的一种潜在危险的方法。 必须注意几点：插拔不能对系统或被插入板造成物理损坏或永久性破坏，而且不能引起数据丢失或任何瞬时系统混乱。 本应用指南从物理方面描述了使用有序接插件将基于 Virtex™-II 的板卡插入系统或系统背板的操作。采用这种方式，在任何信号引脚接触前，VCC 与 GND （地线）可先行良好接触。 热插入部分还介绍了使用普通无序接插件的风险。 此应用指南中未涉及诸如探测卡存在与否或系统对板卡的接纳程度等系统问题。早期中文版

This application note describes a system using the Virtex™-5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-5 ML505 development board.

This Virtex™-5 application note describes an SFI-4.1 interface, a 16-channel, source-synchronous LVDS interface operating at SDR. The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input.The timing of the receiver is described in depth and characterized in hardware.

This application note describes how to use a Virtex™-5 device to interface to Common I/O(CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices.

The application discusses the use of the Xilinx® Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex®-5 I/O 都具有的输入串行器/解串器（ISERDES）和输出双数据速率（ODDR）特性。

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

The non-integer data recovery unit (NI-DRU) presented in this application note is specifically designed for RocketIO™ GTP and GTX transceivers in Virtex®-5 LXT, SXT, TXT, and FXT platforms and consists of look-up tables (LUTs) and flip-flops. The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

本应用指南重点介绍了正交调幅 (QAM) 信号的基带解调，特别描述了分数率抽取电路模块的使用。 本应用指南也对多相抽取滤波器结构进行了简介，讨论了分数率抽取电路及如何使用 Xilinx System Generator 8.1i 实现它，并给出了实现结果。早期中文版

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The design takes advantage of the Virtex™-5 I/O ChipSync™ features ability to adjust the delay of the receiver datapaths creating dynamic setup/hold timing for each device at initialization, compensating for skews associated with the manufacturing process. The receiver operates at 1:8 deserialization on each of the 16 data channels.

This application note describes the implementation and timing details of a four-word burst Quad Data Rate (QDR II) SRAM interface for Virtex®-5 devices.

This application note discusses Linux Operating System debugging techniques. Debugging boot issues, kernel panics, software and hardware debuggers, driver <-> application interaction, and various other tools are discussed.

This application note describes the controller and the data capture technique for high-performance DDR3 SDRAM interfaces. This data capture technique uses the Input Double Data Rate (IDDR) and Output Double Data Rate (ODDR) features available in every Virtex™-5 FPGA I/O.

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express®.

This application note describes how to use the Virtex®-5 FPGA input/output delay (IODELAY) primitive as a means to create a high-precision adjustable oscillator with a wide tuning range. Three different use models are described for the adjustable oscillator:

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

本应用指南就在增量设计流程中使用分区技术进行了讨论。 建议将逻辑密度高的模块实例、时序关键通路或时序关键模块实例划归为分区。

本应用指南描述了如何将 Texas Instruments (TI) ADS6000 系列、带有串行化 LVDS 输出的高速模数转换器 (ADC) 器件与配置成 LVDS 输入的 Virtex™-4 或 Virtex-5 I/O 接口。

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan™-DSP and Virtex™-5 FPGAs.

The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.

This application note explains the techniques to support SATA initialization in the GTP transceiver of the Virtex™-5 LXT platform.

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

本技术文档详细介绍了在针对电信应用的 Virtex™ 和 Spartan™ FPGA 内实现的数字 PLL 的设计方案。对 PLL 的性能和回路稳定性进行了评估。

描述了用于 RAID6 奇偶生成/数据恢复控制器的硬件加速器，以及 ECC 和 MIG DDR2 控制器。

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

Virtex™-5 devices have a high-precision programmable delay element (IDELAY) associated with every input pin. This application note shows how to implement 8X oversampling of many data streams using a single DCM, two global clock resources, and minimal FPGA logic resources. This solution provides better jitter tolerance than techniques using multiple DCMs. When paired with a suitable data recovery scheme, this oversampling technique can be used with many different data protocols up to 550 Mb/s. A reference design is included that implements a SD-SDI (SMPTE 259M) receiver running at 270 Mb/s.

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The receiver operates at 1:6 deserialization on each of the 16 data channels. Similar to XAPP855, the design also includes a real-time window monitoring circuit for added performance. This reference design calibrates and compensates for skews associated with process, voltage, and temperature (PVT) at initialization and dynamically during operation.

本应用指南就利用 LogiCORE™ 解决方案实现的 PCI-X 设计的动态总线模式重配置进行了讨论。 它说明了如何在加电之后，利用 CPLD 对 Virtex™-4 和 Virtex-5 FPGA 进行动态的重新加载操作，以便对支持 PCI-X 和 PCI 兼容性的 FPGA 进行动态重配置。

本应用指南提供了一个关于如何使用 Virtex™-5 LXT FPGA 中用于 PCI Express® 设计的集成端点模块实现点到点（FPGA 到 FPGA）高速串行包传输功能的参考设计。

本应用指南描述了“纠错控制”(Error Correction Control, ECC) 模块在 Virtex™-II、Virtex-II Pro、Virtex-4 和 Virtex-5 器件中的实现。 该设计可检测和纠正全部单位元错误 (single bit error)（在由 64 位数据和 8 个校验位或由 32 位数据和 7 个校验位组成的代码字内），并可以检测数据中的双位元错误 (double bit error)。 设计采用的是汉明码 (Hamming code)，这是用于 ECC 操作的一种简单而高效的代码。 因此，该设计的性能卓越，并能提供非常高的资源利用率。

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

Document provides a discussion of strategies and representative calculations for handling single event upsets (SEUs) with an emphasis on reliability when addressing these low probability events.

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express® core. C code running on the PowerPC® 440 drives the EDK system.

描述了用于 RAID6 奇偶生成/数据恢复控制器的硬件加速器，以及 ECC 和 MIG DDR2 控制器。

To communicate that Xilinx is discontinuing certain Development Systems Products.

This user guide provides a detailed description of each component and peripheral available on the ML501 Evaluation Platform. The ML501 board is a low-cost, entry-level platform for evaluation of Virtex®-5 LX FPGAs.

This user guide showcases various features of the Virtex®-5 FXT FPGA ML507 development board. It describes the hardware platform, the HelloWorld software application, and the BlueCat Linux images.

This guide describes the Virtex®-5 FPGA RocketIO™ Transceiver Signal Integrity Simulation (SIS) Kit for Synopsys HSPICE.

This signal integrity simulation kit provides a simulation environment for users to evaluate their channel designs with the Virtex®-5 FPGA RocketIO™ GTX transceivers. This document explains how to use the examples provided in the design kit and helps users modify them for their own needs.

The ML505/ML506/ML507 Getting Started Tutorial provides step-by-step instructions for setting up and using the Virtex®-5 ML505, ML506, and ML507 Evaluation Platforms. These boards come with a number of pre-installed demonstrations. This tutorial guides you through these demonstrations and provides instructions to run them on the ML50x boards.

The ML50x boards enable designers to investigate and experiment with features of Virtex®-5 FPGAs. This user guide describes the features and operation of the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.

本用户指南介绍了 Virtex®-5 LXT、SXT 和 FXT 原型平台的特性与操作方法，并且描述了如何配置 FPGA 链和串行 PROM。

本辅导资料针对 Virtex™-5 ML501 评估平台的使用和设置提供渐进说明。 ML501 平台带有许多预装的演示和设置的程序。 这些程序适用于 System ACE 界面、Platform Flash 和 SPI Flash。 本技术文档是从设置到演示的各个步骤对设计者进行了指导。

本用户指南介绍了几个利用 ML501 评估平台来演示 Virtex™-5 LX 器件特性的设计。

本用户指南描述了 Virtex™-5 LXT 系列 RocketIO™ 特性描述平台（包括 ML521、ML523 和 ML525 板）的特性和操作方法。

本用户指南介绍了 Virtex™-5 插槽式开发平台的特点和操作方法。 插槽板可以容纳不同封装和速度级别的 Virtex-5 LX 器件。 所有现有的 I/O 板上扩展部分“Pin Breakout Area”都提供方便进行 FPGA 测试的探测和分析。

This user guide describes the Virtex®-5 FPGA ML550 Networking Interfaces board, which is the heart of the Virtex-5 FPGA ML550 Source-Synchronous Interfaces Tool Kit.

本用户指南介绍了用于 PCI 和 PCI Express 设计的 Virtex™-5 ML555 开发套件。

XGI SuperClock 模块用户指南概述了 SuperClock 模块附加板的功能、操作和配置。

Virtex™-5 ML561 存储器接口工具套件提供了一个完整的开发平台以便与外部存储器器件连接，进而在 Virtex-5 LXT 平台 FPGA 基础上实现设计和验证应用。

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

All package files are ASCII files in zip format.

This document is a brief introduction to the features of the Virtex®-5 devices. It contains the device summary, packaging options, and ordering information.