Virtex-5 FPGA Characterization Reports

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Fibre Channel specifications.

本报告描述了 Virtex™-5 GTP 收发器相对于通用公共无线电接口 (CPRI) 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 PCI Express 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 OC-48 各项指标的电气特性描述测试。

本报告描述了 GTP 收发器相对于 10 Gb 连接单元接口 (XAUI) 指标的电气性能特性描述测试。

本报告描述了 GTP 收发器相对于千兆位级以太网串行协议标准的电气特性描述测试。

This report documents the results of characterization performed on the Virtex™-5 Clock Management Tile(CMT) that combines two enhanced Digital Clock Managers (DCMs) with one Phase-Locked Loop (PLL), and clocking resources.

本特性描述报告提供了 Virtex®-5 LXT 和 SXT RocketIO™ GTP 收发器在指定工艺、电压和温度（PVT）条件下的 FPGA 特性描述结果。

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Serial ATA Generation 2 (3 Gb/s) specification.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-4 RocketIO™ MGT.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-II Pro RocketIO™ MGT.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against OIF-CEI-02.0, "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O".