XC3000

本应用指南介绍了使用 Alliance 系列软件实现 HDL 仿真时需注意的基本流程和问题。 本技术文档的目的是让用户熟悉一些概念，它不可替代 Xilinx 或 HDL 仿真器的技术文档。

本应用指南介绍了成熟的Xilinx产品系列，并着重讲述了其相互区别。

在Spartan™ XC3000、XC4000和XC5200器件系列中，Xilinx提供了现场可编程门阵列（FPGA）的扩展和兼容产品。本简介介绍了Xilinx FPGA的2方面：给客户提供了哪些逻辑资源，以及如何对器件进行编程。

Clarifies why the overshoot/undershoot limit includes both magnitude and duration. Applies to mature FPGA families only.

Beware of hold time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates.

All Xilinx SRAM-based FPGAs can be in-system configured and reconfigured an unlimited number of times. This application note describes the procedures for reconfiguring mature Xilinx FPGAs.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGA 可在普通的菊花链结构中进行配置，在那里主器件生成 CCLK 脉冲，并将串行配置信息输入下一个下行器件，该下行器件进一步将数据输入下一个下行器件，以此类推。 菊花链中的器件数量没有限制，XC3000™、XC4000™、Spartan™ 和 XC5200™ 系列器件可以自由组合，但只有一个约束条件：主器件需为该链中最高位系列的器件之一。

这些指南针对所有 XC3000™、XC4000™、XC5200™ 和 Spartan™ FPGA 器件及其衍生产品介绍了配置步骤。一般用户无须了解或记住所有细节，但出现问题时应参考调试提示。

This application note reviews the differences between the XC5200™ and XC2000™/XC3000™ families, recommends approaches for converting XC2000/XC3000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

This application note defines three metrics to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. It also describes the methodology used to determine these values.

This application note discusses binary-to-BCD and BCD-to-binary conversions that are performed between serial binary values and parallel BCD values.

The phase comparator described in this application note permits phase-locked loops to be constructed using FPGA devices that require only an external voltage-controlled oscillator and integrating amplifier.

本应用指南讨论了在 FPGA 器件中实现状态机的多种现有方法，特别是针对中型状态机的一位热码编码方法。

This application note contains additional information for designing with the XC3000™ series of FPGA devices. This information supplements the data sheets, and is provided for guidance only.

This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small longline delay is eliminated, resulting in the fastest possible synchronous counter.

简单状态机用于调整2个光电管的输出，以便控制上/下计数器。状态机提供了滞后功能以便正确计算元件数量，而不管方向的变化。

A simple algorithm is described for determining the depth of logic, in CLBs, that can be supported at a given clock frequency. The algorithm is suitable for XC3000 Series or XC4000 Series FPGA devices.

Harmonic Frequency Synthesizer: Uses an accumulator technique to generate frequencies that are evenly spaced harmonics of some minimum frequency. Extensive pipelining is employed to permit high clock rates. FSK Modulator: A modification of the Harmonic Frequency Synthesizer that automatically switches between two frequencies in accordance with an NRZ input.

CLBs are used to emulate IEEE 1149.1 Boundary Scan. The FPGA device is configured to test the board interconnect, and then reconfigured for operation.

CLBs are used to emulate IEEE 1149.1 Boundary Scan. The FPGA device is configured to test the board interconnect, and then reconfigured for operation.

While XC3000 series FPGA devices do not provide RAM, it is possible to construct small register-based FIFOs. A basic synchronous FIFO requires one CLB for each two bits of FIFO capacity, plus one CLB for each word in the FIFO. Optional asynchronous input and output circuits are provided. Design files are available for two implementations of this design. The fastest of the two implementations uses a constraints file to achieve better placement.

The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter. Up, down and up/down counters are described, with lengths of 16 and 32 bits. Design files are available for all six versions.