XC3000

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGA 可在普通的菊花链结构中进行配置，在那里主器件生成 CCLK 脉冲，并将串行配置信息输入下一个下行器件，该下行器件进一步将数据输入下一个下行器件，以此类推。 菊花链中的器件数量没有限制，XC3000™、XC4000™、Spartan™ 和 XC5200™ 系列器件可以自由组合，但只有一个约束条件：主器件需为该链中最高位系列的器件之一。

这些指南针对所有 XC3000™、XC4000™、XC5200™ 和 Spartan™ FPGA 器件及其衍生产品介绍了配置步骤。一般用户无须了解或记住所有细节，但出现问题时应参考调试提示。

This application note defines three metrics to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. It also describes the methodology used to determine these values.

This application note contains additional information for designing with the XC3000™ series of FPGA devices. This information supplements the data sheets, and is provided for guidance only.