Recorded E-Learning Course Listing

We provide Recorded e-Learning for course accessibility at your convenience. Available at no charge, topics range from high-level software updates and ASIC to FPGA conversion strategies to specifics on device architecture. Check one out today!

DSP Design
CPLD Design
Languages

FPGA Design
Embedded Design
Connectivity Design

FPGA Design Courses

Basic FPGA Configuration - Launch (login required)

After completing this 50-minute, two-module course, you will be able to describe the FPGA configuration pins, choose an appropriate FPGA configuration scheme, connect multiple FPGAs into a configuration daisy chain, and describe currently available prototyping hardware.

Basic FPGA Architecure: Architecture Wizard and the Floorplan Editor - Launch (login required)

After completing this 30-minute course, you will be able to list at least two uses for the Architecture Wizard, identify two features of the Floorplan Editor, and create quality pin assignments for Xilinx FPGAs.

Basic FPGA Architecure: Memory and Clocking Resources - Launch (login required)

After completing this 30-minute course, you will be able to identify the basic memory and clocking resources of Virtex®-5 FPGAs, list their dedicated resources, and list some of the differences between Spartan®-3 and Virtex®-5 FPGAs.

Basic FPGA Architecture: Slice and I/O Resources - Launch (login required)

After completing this 30-minute course, you will be able to describe the basic slice and I/O resources available in Virtex-5 FPGAs.

ChipScope™ Pro Software (with labs) - Launch (login required)

After completing this 24-minute course, you will be able to describe the value of the ChipScope™ Pro software, describe how it works, list available relevant cores, use the Core Generator and Core Inserter software, plan for debug, and debug with the ChipScope Pro software.

Spartan®-3E FPGA Architecture - Launch (login required)

After completing this 43-minute course, you will be able to describe how the architecture of the Spartan™-3E FPGA differs from the architecture of the Spartan-3 FPGA, determine if the Spartan-3E FPGA architecture fits your application requirements, and describe the new features of the Spartan-3E FPGA platform.

Spartan®-3 FPGA Architecture Overview - Launch (login required)

After completing this 31-minute course, you will be able to describe the Spartan™-3 architecture, its underlying technology and target markets, as well as its design entry, implementation, and verification software support features. You will also be able to describe the system solutions for DSP, MicroBlaze™ embedded processor, and communications connectivity.

Spartan®-3 HDL Coding Techniques (Part 1) - Launch (login required)

After completing this 30-minute module, you will be able to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.

Spartan®-3 HDL Coding Techniques (Part 2) - Launch (login required)

After completing this 30-minute module, you will be able to code properly for carry logic and memory resources. You will also be able to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.

Virtex®-5 FPGA HDL Coding Techniques (Part 1) - Launch (login required)

After completing this 30-minute module, you will be able to code properly for Virtex®-5 FPGA register resources. You will also be able to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possible.

Virtex®-5 FPGA HDL Coding Techniques (Part 2) - Launch (login required)

After completing this 30-minute module, you will be able to code properly for 6-input LUT and block RAM resources in the Virtex®-5 FPGA. You will also be able to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex®-5 FPGA.

Global Timing Constraints - Launch (login required)

After completing this 15-minute course, you will be able to apply global timing constraints to a simple synchronous design and use the Constraints Editor to specify global timing constraints.

Area Constraints - Launch (login required)

After completing this 27-minute course, you will be able to make an effective layout with area constraints, uUse area constraints to improve the speed of your design by grouping critical paths, use area constraints to localize (and maximize) your designs clocks, and use area constraints in an incremental design flow.

Timing Closure Flow - Launch (login required)

After completing this 71-minute course, you will be able to describe the overall flow for achieving timing closure, specify the key elements in achieving timing closure, describe the importance of cores and coding for performance, list some of the key implementation options in timing closure, and state where to learn more about each step in the timing closure flow.

Achieving Breakthrough Performance in Virtex®-4 FPGAs - Launch (login required)

After completing this 57-minute course, you will be able to describe Virtex®-4 FPGA advantages, discuss how to achieve optimum FPGA performance, and describe the Virtex®-4 FPGA performance comparison methodology.

Clocking Techniques for Virtex®-II FPGAs - Launch (login required)

After completing this 34-minute course, you will be able to describe the features and limitations of the DCM, BUFGMUX, and global routing resources, and explain how to build a clock assignment strategy for your design.

SPI-4.2 - Launch (login required)

After completing this 38-minute course, you will be able to identify the basics of the OSI 7 Layer Model, describe the protocol, specifications, and competitive advantages of the SPI-4.2 solution, and explain how the SPI-.2 solution fits into the OSI 7 Layer Model.

IC Packaging - Launch (login required)

After completing this 41-minute course, you will be able to determine the IC package that best meets your design goals, lList the various sources of heat generation in IC packages, identify and define critical thermal variables, and discuss Xilinx-provided specs to manage your thermal budget.

Xilinx ISE Design Suite 10.1 Software Tutorials - Launch

The objective of the ISE™ Design Suite 10.1 Tutorials modules is to familiarize you with the Xilinx design flow. The state-of-the art tutorials take you from design entry to verification and debugging using the Watch design targeting a Spartan™-3A device.

DDR-I SDRAM Memory Interface - Launch (login required)

After completing this 35-minute course, you will be able to list the Virtex®-II and Virtex®-II Pro device features that enable high-speed memory interface design, calculate timing margins for the Virtex®-II series DDR-I interface design, and access memory resources on the Xilinx website, including the Xilinx Memory Tool Kit.

ASIC User (with labs)

Launch FPGA and ASIC Technology Comparison module

Launch FPGA vs. ASIC Design Flow (no lab) module

Launch ASIC to FPGA Coding Conversion (includes lab) module

After completing this course, you will be able to describe the differences between FPGAs and ASICs as they relate to basic technology features and the impact of those features on coding style, implementation, and product selection, as well as design flows, and coding conversion.

Connectivity Design Courses

PCI Express - Launch (login required)

After completing this 45-minute course, you will be able to explain the background behind PCI Express, identify the differences between PCI and PCI Express, and describe a basic PCI Express Link, the different layers of a PCI Express device, and the Xilinx PCI Express solution.

Embedded Design Courses

EDK Tutorials - Launch

The objective of the tutorial modules is to familiarize you with the new and improved Xilinx design flows from design entry to verification and debugging.

DSP Design Courses

System Generator Getting Started - Launch (login required)

After completing this 40-minute course, you will be able to create a DSP design that includes memories and control using Simulink and implement that design into a Xilinx FPGA, design highly efficient FIR filters for Xilinx device architectures, and define fixed-point numeric precision abstractly using the Xilinx DSP blockset.

AccelDSP™ Jump Start Modules - Launch (login required)

After completing this 50-minute course, you will be able to modify a MATLAB script for a DSP algorithm for synthesis using the AccelDSP Synthesis Tool, identify the concepts of quantization as well as specify, monitor, and control bit growth in a MATLAB design, and apply MATLAB coding style changes and AccelDSP directives to optimize a design for performance and efficiency.

CPLD Design Courses

CoolRunner™-II CPLD: Clocking and I/O - Launch (login required)

After completing this 15-minute course, you will be able to describe the clock divider and DualEDGE features of CoolRunner™-II CPLDs, list applications that can benefit from these clocking features, and describe several solutions for special signaling and interface requirements.

Languages

Basic HDL Coding Style (Part 1) - Launch (login required)

This Basic HDL Coding Style, part 1 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow and explains proper coding techniques for combinatorial and registered logic. Microsoft Windows Media Player 8 or later is required to view this module.

Basic HDL Coding Style (Part 2) - Launch (login required)

This Basic HDL Coding Techniques, part 2 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow, including Finite State Machine design and building pipeline stages. Microsoft Windows Media Player 8 or later is required to view this module.