Recorded Lecture: Virtex-5 FPGA HDL Coding Techniques
Part 1 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code properly for Virtex-5 FPGA register resources
- To manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possible
Launch Part 1
Part 2 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA
- To manage your control signal usage so that you can build a high-speed FPGA design
- You will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA
Launch Part 2
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