Recorded Lecture: Spartan-3 FPGA HDL Coding Techniques
Part 1 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code properly for FPGA registers, SRLs, and other dedicated resources
- To build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs
Launch Part 1
Part 2 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code properly for carry logic and memory resources
- To manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs
Launch Part 2
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