Recorded Lecture: Virtex-6 & Spartan-6 FPGA HDL Coding Techniques
Part 1 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code your register resources so your design will have fewer control sets and run at a higher system speed
- Avoid the most common coding mistakes that reduce device utilization and system speed
- Anticipate how your design will map to the register resources
Launch Part 1
Part 2 Description
Duration: approximately 30 mins.
After completing this module, you will be able to
- Code your design so you can infer more of the dedicated hardware resources
- Avoid the most common coding mistakes which hurt device utilization
- Reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR)
Launch Part 2
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