After completing this workshop, you will be able to:

• Understand high-level synthesis flow of Vivado HLS
• Apply directives to optimize design performance 
• Perform system-level integration of blocks generated by the Vivado HLS tool

Day 1:

• Introduction to HLS
• Using Vivado HLS
• Lab 1: Creating Project and Understanding Reports
  • Experience a basic design flow of Vivado HLS and review generated output.
• Improving Performance
• Lab 2: Optimizing Performance through Pipelining
  • Use pipelining technique to improve performance.
• Data Types

Day 2:

• Optimizing for Area and Resources
• Lab 3: Improving Area and Resource Utilization
  • Use directives to optimize resource sharing.
• Handling Block- and Port-Level Protocols
• Coding Considerations
• Creating a Processor System
• Lab 4: Designing an Audio System
  • Use IP-XACT export capability of Vivado HLS to generate an IP and integrate the generated core in an embedded system developed using IP Integrator.