This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite
Additional Learning Materials
| User Guides | Date |
|---|---|
 UltraScale Architecture PCB Design Guide | 06/26/2019 |
| UltraScale Architecture SelectIO Resources User Guide | 01/16/2019 |
| UltraScale Architecture Clocking Resources User Guide | 12/19/2018 |
| Vivado Design Hubs | Date |
 I/O and Clock Planning | 05/15/2019 |
| Designing with IP | 05/15/2019 |
| Using IP Integrator | 05/15/2019 |
| Memory Interface Design Tips | Date |
| Migrating Memory IP Using Vivado | 05/22/2019 |
| PCB Trace Derating | 06/26/2019 |
| Using the Memory IP Traffic Generator | 05/22/2019 |
| Targeted Reference Designs | Date |
| Kintex UltraScale FPGA KCU105 Evaluation Kit | 05/15/2019 |
Support Resources
Please visit the Xilinx Service Portal to open or review a service request.
| Solution Centers | Date |
|---|---|
 Xilinx Memory IP Solution Center | 04/26/2016 |
| Design Advisories | Date |
| Design Advisories for Memory Interfaces | 03/13/2017 |
| Known Issues | Date |
| DDR4 UltraScale and UltraScale+ IP Release Notes and Known Issues | 05/29/2019 |
| DDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues | 05/29/2019 |
| Debug Resources | Date |
| Using the Memory Interface Debug GUI and XSDB for Calibration Failures | 05/22/2019 |
| Debugging Data Errors | 05/22/2019 |
 Memory Interface UltraScale Design Checklist | |
| Hardware Debug Guide - Debugging Memory Interface Issues | |
| Forums | Date |
| Xilinx User Community Forums - Memory Interface Generator (MIG) |
