Throughput and Latency for Soft-Decision FEC v1.1

Vivado Design Suite Release 2023.2

Table of Contents

• LDPC Throughput and Latency
• 5G New Radio - Decode
• 5G New Radio - Encode
• WiFi 802.11ac - Decode
• WiFi 802.11ac - Encode
• DOCSIS 3.1 - Decode
• DOCSIS 3.1 - Encode
• Turbo Decode Throughput

LDPC Throughput and Latency

Throughput is measured in terms of information bits per second, including any punctured bits. In the following sections, the throughput has been measured by inputting the data as quickly as possible. The tables provide the time of the start and end of the first input block and the start and end of the output data of the first, 84^th, 96^th and 100^th blocks, relative to the start of the first block that was input. Initial Latency is the time between the last transfer of the first input block and the last output of the first output block. The assumption here is that the LDPC code parameters and shared LDPC code parameters in the SD-FEC hard block are already configured for the particular code. Final throughput is the throughput from blocks 84 to 96. Note that the number 12 has been used, as this is a multiple of 1, 2, 3 and 4, which is the number of blocks that can be decoded simultaneously. The assumptions are that the output is not held up and that the decoder measurement is performed with hard output that does not include parity.

Note that the latency of later blocks is likely to be greater than the initial latency due to input buffering holding additional blocks, and can often be reduced by feeding in the blocks at a steady rate, commensurate with the throughput, to avoid them building up in the input buffer. It is also possible, for some codes, to have a reduced latency with a small reduction in throughput, because of the way the core schedules multiple blocks, and lower throughput can mean fewer blocks interleaved and lower latency as a result.

In the following tables, clock frequencies of 667 MHz on core_clk and 400 MHz on other clocks are assumed, and the decoder uses eight iterations. However, for details on the clock frequency supported by a device and resource utilization, visit the Performance and Resource Utilization web page. Packing is assumed to be enabled; if disabled, then for codes with PSIZE ≤ 64 there is likely to be a significant throughput reduction.

5G New Radio - Decode

5G New Radio - Encode

In 5G NR mode, the 5G support logic generates and downloads LDPC Code and Shared LDPC Code Parameters for the code definition applied through the CTRL interface. The download latency in each case is provided in the table below. For throughput enhancement, write the code definitions through the CTRL interface as early as possible compared to the input data to minimize the impact of code latency and enhance throughput. However, care must be taken not to apply more CTRL words than the corresponding code blocks in a given transmission time interval.

The 5G support logic also keeps log of, at most, 14 codes downloaded to the SD-FEC core at any given time to avoid the need to regenerate and re-download the same code.

WiFi 802.11ac - Decode

WiFi 802.11ac - Encode

DOCSIS 3.1 - Decode

DOCSIS 3.1 - Encode

Turbo Decode Throughput

The figure below illustrates the maximum achievable Turbo Decode throughput for a given block size.

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