Performance and Resource Utilization for AXI BRAM Controller v4.1

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Virtex-7

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	DATA_WIDTH	ID_WIDTH	PROTOCOL	SUPPORTS_NARROW_BURST	SINGLE_PORT_BRAM	USE_ECC	FAULT_INJECT	ECC_ONOFF_RESET_VALUE	BMG_INSTANCE	MEM_DEPTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7v2000t	flg1925	-2	axi_bram_ctrl_1	32	0	AXI4	0	0	0	0	0	EXTERNAL	8192	s_axi_aclk	438	309	278	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_10	32	0	AXI4LITE	0	1	0	0	0	EXTERNAL	8192	s_axi_aclk	946	37	12	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_2	64	0	AXI4	0	0	0	0	0	EXTERNAL	8192	s_axi_aclk	407	310	378	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_3	128	0	AXI4	0	0	0	0	0	EXTERNAL	8192	s_axi_aclk	446	340	579	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_4	256	0	AXI4	0	0	0	0	0	EXTERNAL	8192	s_axi_aclk	423	397	979	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_5	512	0	AXI4	0	0	0	0	0	EXTERNAL	8192	s_axi_aclk	415	522	1779	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_6	32	0	AXI4	0	1	0	0	0	EXTERNAL	8192	s_axi_aclk	469	202	203	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_7	64	0	AXI4	0	1	0	0	0	EXTERNAL	8192	s_axi_aclk	423	216	303	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_8	128	0	AXI4	0	1	0	0	0	EXTERNAL	8192	s_axi_aclk	423	256	503	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-2	axi_bram_ctrl_9	512	0	AXI4	1	0	0	0	0	INTERNAL	32768	s_axi_aclk	173	1028	1935	0	512	0	PRODUCTION 1.10 2014-09-11

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