Performance and Resource Utilization for AXI Clock Converter v2.1

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PROTOCOL
READ_WRITE_MODE
DATA_WIDTH
ID_WIDTH
ACLK_ASYNC
SYNCHRONIZATION_STAGES
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7a200t fbg676 2 axi4_mi_7a2 AXI4 READ_WRITE 1024 4 1 3 s_axi_aclk=100 m_axi_aclk 318 1749 5130 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 2 axi4_si_7a2 AXI4 READ_WRITE 1024 4 1 3 m_axi_aclk=100 s_axi_aclk 318 1744 5130 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 2 axi4lite_mi_7a2 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 599 49 508 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 2 axi4lite_mi_7a20 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 599 49 508 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 2 axi4lite_si_7a2 AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 611 49 508 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 2 axi4lite_si_7a20 AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 611 49 508 0 0 0 PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PROTOCOL
READ_WRITE_MODE
DATA_WIDTH
ID_WIDTH
ACLK_ASYNC
SYNCHRONIZATION_STAGES
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 2 axi4_mi_7k2 AXI4 READ_WRITE 1024 4 1 3 s_axi_aclk=100 m_axi_aclk 475 1764 5130 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 axi4_si_7k2 AXI4 READ_WRITE 1024 4 1 3 m_axi_aclk=100 s_axi_aclk 487 1757 5130 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 axi4lite_mi_7k2 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 868 50 508 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 axi4lite_mi_7k32 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 868 50 508 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 axi4lite_si_7k2 AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 845 50 508 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 axi4lite_si_7k32 AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 845 50 508 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PROTOCOL
READ_WRITE_MODE
DATA_WIDTH
ID_WIDTH
ACLK_ASYNC
SYNCHRONIZATION_STAGES
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku085 flva1517 2 axi4_mi_ku2 AXI4 READ_WRITE 1024 4 1 3 s_axi_aclk=100 m_axi_aclk 599 1539 5130 0 0 0 PRODUCTION 1.26 12-04-2018
xcku040 ffva1156 2 axi4lite_mi_ku040 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 1038 57 508 0 0 0 PRODUCTION 1.25 12-04-2018
xcku085 flva1517 2 axi4lite_mi_ku2 AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 956 54 508 0 0 0 PRODUCTION 1.26 12-04-2018
xcku040 ffva1156 2 axi4lite_si_ku040 AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 1056 52 508 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PROTOCOL
READ_WRITE_MODE
DATA_WIDTH
ID_WIDTH
ACLK_ASYNC
SYNCHRONIZATION_STAGES
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku5p ffvb676 2 axi4_mi_ku5p AXI4 READ_WRITE 1024 1 3 s_axi_aclk=100 m_axi_aclk 663 1518 5098 0 0 0 PRODUCTION 1.29 05-01-2022
xcku5p ffvb676 2 axi4_si_ku5p AXI4 READ_WRITE 1024 1 3 m_axi_aclk=100 s_axi_aclk 622 1519 5098 0 0 0 PRODUCTION 1.29 05-01-2022
xcku5p ffvb676 2 axi4lite_mi_ku5p AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 1308 55 509 0 0 0 PRODUCTION 1.29 05-01-2022
xcku5p ffvb676 2 axi4lite_si_ku5p AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 1419 55 509 0 0 0 PRODUCTION 1.29 05-01-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PROTOCOL
READ_WRITE_MODE
DATA_WIDTH
ID_WIDTH
ACLK_ASYNC
SYNCHRONIZATION_STAGES
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 2 axi4_mi_zu9e AXI4 READ_WRITE 1024 1 3 s_axi_aclk=100 m_axi_aclk 658 1516 5098 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 axi4_si_zu9e AXI4 READ_WRITE 1024 1 3 m_axi_aclk=100 s_axi_aclk 710 1522 5098 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 axi4lite_mi_zu9e AXI4LITE READ_WRITE 64 1 3 s_axi_aclk=100 m_axi_aclk 1220 55 508 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 axi4lite_si_zu9e AXI4LITE READ_WRITE 64 1 3 m_axi_aclk=100 s_axi_aclk 1355 57 508 0 0 0 PRODUCTION 1.30 05-15-2022

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