Resource Utilization for UltraScale+ 100G Ethernet Subsystem v3.1

Vivado Design Suite Release 2020.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CMAC_CAUI4_MODE
GT_TYPE
GT_REF_CLK_FREQ
ENABLE_AXIS
TX_OTN_INTERFACE
ENABLE_TIME_STAMPING
TX_PTP_1STEP_ENABLE
INCLUDE_RS_FEC
INCLUDE_AUTO_NEG_LT_LOGIC
ENABLE_AXI_INTERFACE
ENABLE_PIPELINE_REG
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu3p ffvc1517 -2 caui10_gty 0 GTY 161.1328125 0 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 188 2426 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui10_gty_axis 0 GTY 161.1328125 1 0 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 1543 3686 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty 1 GTY 161.1328125 0 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 153 2276 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_anlt 1 GTY 161.1328125 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 12832 10742 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_axi 1 GTY 156.25 1 1 drp_clk=100 gt_ref_clk_p=156 init_clk=100 rx_clk=322 s_axi_aclk=100 6681 26864 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_rsfec_ptp_1step 1 GTY 161.1328125 1 1 1 0 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 153 2276 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_rsfec_ptp_2step 1 GTY 161.1328125 1 2 1 0 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 153 2276 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_tx_otn 1 GTY 161.1328125 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 12740 23741 0 0 9 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 caui4_gty_tx_otn_rsfec 1 GTY 161.1328125 1 1 drp_clk=100 gt_ref_clk_p=161 init_clk=100 rx_clk=322 25899 36187 0 0 9 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 rs10to4_gty 2 GTY 161.1328125 0 1 drp_clk=100 gt_drpclk=100 init_clk=100 qpll0clk_in[0]=322 qpll0clk_in[1]=322 qpll0clk_in[2]=322 qpll0clk_in[3]=322 qpll0clk_in[4]=322 qpll0clk_in[5]=322 qpll0clk_in[6]=322 qpll0clk_in[7]=322 qpll0clk_in[8]=322 qpll0clk_in[9]=322 qpll0refclk_in[0]=322 qpll0refclk_in[1]=322 qpll0refclk_in[2]=322 qpll0refclk_in[3]=322 qpll0refclk_in[4]=322 qpll0refclk_in[5]=322 qpll0refclk_in[6]=322 qpll0refclk_in[7]=322 qpll0refclk_in[8]=322 qpll0refclk_in[9]=322 qpll1clk_in[0]=322 qpll1clk_in[1]=322 qpll1clk_in[2]=322 qpll1clk_in[3]=322 qpll1clk_in[4]=322 qpll1clk_in[5]=322 qpll1clk_in[6]=322 qpll1clk_in[7]=322 qpll1clk_in[8]=322 qpll1clk_in[9]=322 qpll1refclk_in[0]=322 qpll1refclk_in[1]=322 qpll1refclk_in[2]=322 qpll1refclk_in[3]=322 qpll1refclk_in[4]=322 qpll1refclk_in[5]=322 qpll1refclk_in[6]=322 qpll1refclk_in[7]=322 qpll1refclk_in[8]=322 qpll1refclk_in[9]=322 rx_clk=322 185 3556 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu3p ffvc1517 -2 rs10to4_gty_axi 2 GTY 161.1328125 1 1 drp_clk=100 gt_drpclk=100 init_clk=100 qpll0clk_in[0]=322 qpll0clk_in[1]=322 qpll0clk_in[2]=322 qpll0clk_in[3]=322 qpll0clk_in[4]=322 qpll0clk_in[5]=322 qpll0clk_in[6]=322 qpll0clk_in[7]=322 qpll0clk_in[8]=322 qpll0clk_in[9]=322 qpll0refclk_in[0]=322 qpll0refclk_in[1]=322 qpll0refclk_in[2]=322 qpll0refclk_in[3]=322 qpll0refclk_in[4]=322 qpll0refclk_in[5]=322 qpll0refclk_in[6]=322 qpll0refclk_in[7]=322 qpll0refclk_in[8]=322 qpll0refclk_in[9]=322 qpll1clk_in[0]=322 qpll1clk_in[1]=322 qpll1clk_in[2]=322 qpll1clk_in[3]=322 qpll1clk_in[4]=322 qpll1clk_in[5]=322 qpll1clk_in[6]=322 qpll1clk_in[7]=322 qpll1clk_in[8]=322 qpll1clk_in[9]=322 qpll1refclk_in[0]=322 qpll1refclk_in[1]=322 qpll1refclk_in[2]=322 qpll1refclk_in[3]=322 qpll1refclk_in[4]=322 qpll1refclk_in[5]=322 qpll1refclk_in[6]=322 qpll1refclk_in[7]=322 qpll1refclk_in[8]=322 qpll1refclk_in[9]=322 rx_clk=322 s_axi_aclk=100 6751 28131 0 0 0 PRODUCTION 1.27 02-28-2020

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CMAC_CAUI4_MODE
GT_TYPE
GT_REF_CLK_FREQ
ENABLE_AXIS
TX_OTN_INTERFACE
ENABLE_TIME_STAMPING
TX_PTP_1STEP_ENABLE
INCLUDE_RS_FEC
INCLUDE_AUTO_NEG_LT_LOGIC
ENABLE_AXI_INTERFACE
ENABLE_PIPELINE_REG
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu29p fsga2577 -2 gaui2_gtm 3 GTM drp_clk=100 gt_drpclk=100 gt_ref_clk_p=156 init_clk=100 rx_clk=322 18076 26253 70 16 0 PRODUCTION 1.29 02-28-2020

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