Performance and Resource Utilization for DSP Macro v1.0

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_1 C C+P C-P CLK 548 2 108 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xc7k480t ffg901 -1 k7_1_3 C+CONCAT By_Tier true true CLK 548 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_4 A*B P+A*B CLK 548 1 10 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 2 42 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 2 42 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_1 C C+P C-P CLK 625 2 106 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xcku115 flva1517 -1 ku_1_3 C+CONCAT By_Tier true true CLK 735 0 0 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_4 A*B P+A*B CLK 625 0 10 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_1 C C+P C-P CLK 829 2 106 1 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xcku13p ffve900 -1 kup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 1 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_4 A*B P+A*B CLK 829 0 10 1 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

These results are preliminary and based on advanced speedfiles in 2020.2. As production speedfiles are made available and QoR tuning has occurred, the performance will improve. The 2021.1 numbers will be more representative of what can be expected in production.

It is also important to compare the same speedgrade and voltage. These numbers are for low voltage -1 speedgrade VC1902, running at 0.7V. Results from other families are running at higher voltages.

Note that for Versal ACAPs, the performance of the adaptable engines are expected to be similar to the PL performance of 16nm devices. Using the hard IP in Versal enables higher overall system level performance or lower overall power consumption.

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvm1802 vfvc1760 1LP ver_1_1 C C+P C-P CLK 673 2 116 1 0 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xcvm1802 vfvc1760 1LP ver_1_3 C+CONCAT By_Tier true true CLK 673 0 0 1 0 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_4 A*B P+A*B CLK 673 0 10 1 0 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 673 2 14 1 0 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 673 2 14 1 0 0 ENGINEERING-SAMPLE 1.04 10-18-2020

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_1 C C+P C-P CLK 548 2 108 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xc7vx690t ffg1157 -1 v7_1_3 C+CONCAT By_Tier true true CLK 548 0 0 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_4 A*B P+A*B CLK 548 1 10 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 2 42 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 2 42 1 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_1 C C+P C-P CLK 625 2 106 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xcvu160 flgb2104 -1 vu_1_3 C+CONCAT By_Tier true true CLK 735 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_4 A*B P+A*B CLK 625 0 10 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_1 C C+P C-P CLK 829 2 106 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xcvu9p flgb2104 -1 vup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_4 A*B P+A*B CLK 829 0 10 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_1 C C+P C-P CLK 829 2 106 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_2 C+CONCAT+PCIN By_Tier true true CLK NOT FOUND NOT FOUND
xczu9eg ffvb1156 -1 zup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_4 A*B P+A*B CLK 829 0 10 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 0 0 PRODUCTION 1.29 08-03-2020

COPYRIGHT

Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.