Resource Utilization for UHD-SDI GT v2.0

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_SDI_MODE
C_DATA_FLOW
C_SDI_LINKS
SupportLevel
C_LINE_RATE
C_EN_PICXO_PORTS
C_GT_TX_DATAWIDTH_INTF_0
C_GT_RX_DATAWIDTH_INTF_0
C_Tx_PLL_Selection_INTF_0
C_Tx_PLL2_Selection_INTF_0
C_Rx_PLL_Selection_INTF_0
C_Rx_PLL2_Selection_INTF_0
C_GT_TX_DATAWIDTH_INTF_1
C_GT_RX_DATAWIDTH_INTF_1
C_Tx_PLL_Selection_INTF_1
C_Rx_PLL_Selection_INTF_1
C_Tx_PLL_Selection_INTF_2
C_Rx_PLL_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_2
C_GT_RX_DATAWIDTH_INTF_2
C_Tx_PLL_Selection_INTF_3
C_Rx_PLL_Selection_INTF_3
C_Tx_PLL2_Selection_INTF_1
C_Rx_PLL2_Selection_INTF_1
C_Tx_PLL2_Selection_INTF_2
C_Rx_PLL2_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_3
C_GT_RX_DATAWIDTH_INTF_3
C_Tx_PLL2_Selection_INTF_3
C_Rx_PLL2_Selection_INTF_3
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku15p ffva1156 3 gt_v1_0__conf_35 Duplex 1 1 12G-SDI false 40 40 1 2 1 2 40 40 1 1 1 1 40 40 1 1 2 2 2 2 40 40 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 825 1070 0 0 0 PRODUCTION 1.28 02-27-2020

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_SDI_MODE
C_DATA_FLOW
C_SDI_LINKS
SupportLevel
C_LINE_RATE
C_EN_PICXO_PORTS
C_GT_TX_DATAWIDTH_INTF_0
C_GT_RX_DATAWIDTH_INTF_0
C_Tx_PLL_Selection_INTF_0
C_Tx_PLL2_Selection_INTF_0
C_Rx_PLL_Selection_INTF_0
C_Rx_PLL2_Selection_INTF_0
C_GT_TX_DATAWIDTH_INTF_1
C_GT_RX_DATAWIDTH_INTF_1
C_Tx_PLL_Selection_INTF_1
C_Rx_PLL_Selection_INTF_1
C_Tx_PLL_Selection_INTF_2
C_Rx_PLL_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_2
C_GT_RX_DATAWIDTH_INTF_2
C_Tx_PLL_Selection_INTF_3
C_Rx_PLL_Selection_INTF_3
C_Tx_PLL2_Selection_INTF_1
C_Rx_PLL2_Selection_INTF_1
C_Tx_PLL2_Selection_INTF_2
C_Rx_PLL2_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_3
C_GT_RX_DATAWIDTH_INTF_3
C_Tx_PLL2_Selection_INTF_3
C_Rx_PLL2_Selection_INTF_3
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu27p figd2104 1 gt_v1_0__conf_37 PICXO Duplex 2 1 3G-SDI true 20 20 2 1 2 1 20 20 2 2 2 2 20 20 2 2 1 1 1 1 20 20 1 1 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 1708 2093 0 0 0 PRODUCTION 1.32 01-20-2021

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_SDI_MODE
C_DATA_FLOW
C_SDI_LINKS
SupportLevel
C_LINE_RATE
C_EN_PICXO_PORTS
C_GT_TX_DATAWIDTH_INTF_0
C_GT_RX_DATAWIDTH_INTF_0
C_Tx_PLL_Selection_INTF_0
C_Tx_PLL2_Selection_INTF_0
C_Rx_PLL_Selection_INTF_0
C_Rx_PLL2_Selection_INTF_0
C_GT_TX_DATAWIDTH_INTF_1
C_GT_RX_DATAWIDTH_INTF_1
C_Tx_PLL_Selection_INTF_1
C_Rx_PLL_Selection_INTF_1
C_Tx_PLL_Selection_INTF_2
C_Rx_PLL_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_2
C_GT_RX_DATAWIDTH_INTF_2
C_Tx_PLL_Selection_INTF_3
C_Rx_PLL_Selection_INTF_3
C_Tx_PLL2_Selection_INTF_1
C_Rx_PLL2_Selection_INTF_1
C_Tx_PLL2_Selection_INTF_2
C_Rx_PLL2_Selection_INTF_2
C_GT_TX_DATAWIDTH_INTF_3
C_GT_RX_DATAWIDTH_INTF_3
C_Tx_PLL2_Selection_INTF_3
C_Rx_PLL2_Selection_INTF_3
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu5ev sfvc784 1 gt_v1_0__conf_31 PICXO Duplex 1 1 3G-SDI true 20 20 1 2 1 2 20 20 1 1 1 1 20 20 1 1 2 2 2 2 20 20 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 861 1050 0 0 0 PRODUCTION 1.29 08-03-2020
xczu5ev sfvc784 1 gt_v1_0__conf_32 PICXO RX_Only 3 1 3G-SDI 20 20 1 2 1 2 20 20 1 1 1 1 20 20 1 1 2 2 2 2 20 20 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 2119 2634 0 0 0 PRODUCTION 1.29 08-03-2020
xczu7eg fbvb900 1LV gt_v1_0__conf_33 Duplex 1 1 6G-SDI false 40 40 1 2 1 2 40 40 1 1 1 1 40 40 1 1 2 2 2 2 40 40 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 832 1070 0 0 0 PRODUCTION 1.29 08-03-2020
xqzu29dr ffrf1760 1 gt_v1_0__conf_34 Duplex 1 1 6G-SDI false 40 40 1 2 1 2 40 40 1 1 1 1 40 40 1 1 2 2 2 2 40 40 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 830 1070 0 0 0 PRODUCTION 1.29 12-02-2020
xqzu28dr ffre1156 2 gt_v1_0__conf_38 PICXO Duplex 1 1 12G-SDI true 40 40 1 2 1 2 40 40 1 1 1 1 40 40 1 1 2 2 2 2 40 40 2 2 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 834 1070 0 0 0 PRODUCTION 1.29 12-02-2020
xczu5ev sfvc784 1 gt_v1_0__conf_39 PICXO Duplex 1 1 3G-SDI true 20 20 2 1 2 1 20 20 2 2 2 2 20 20 2 2 1 1 1 1 20 20 1 1 drpclk_in=100 intf_0_qpll0_refclk_in=149 intf_0_qpll1_refclk_in=148 861 1050 0 0 0 PRODUCTION 1.29 08-03-2020

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