Resource Utilization for 10G/25G Ethernet Subsystem v4.1

Vivado Design Suite Release 2022.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
LINE_RATE
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
GT_LOCATION
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffve1517 2 test_usplus_2_10 10 1 1 0 1 0 1 rx_core_clk_0=156 s_axi_aclk_0=100 tx_core_clk_0=156 9753 16648 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffve1517 2 test_usplus_2_25 25 1 1 0 1 0 1 rx_core_clk_0=391 s_axi_aclk_0=100 tx_core_clk_0=391 9770 16662 0 0 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
LINE_RATE
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
GT_LOCATION
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP test_versal_vsl_1LP_10 10 1 1 0 1 0 1 rx_core_clk_0=156 s_axi_aclk_0=100 tx_core_clk_0=156 10069 18189 0 0 0 PRODUCTION 2.08 2022-03-27
xcvc1902 vsva2197 1LP test_versal_vsl_1LP_25 25 1 1 0 1 0 1 rx_core_clk_0=391 s_axi_aclk_0=100 tx_core_clk_0=391 10431 18198 0 0 0 PRODUCTION 2.08 2022-03-27
xcvc1902 vsva2197 2MP test_versal_vsl_2MP_10 10 1 1 0 1 0 1 rx_core_clk_0=156 s_axi_aclk_0=100 tx_core_clk_0=156 10068 18188 0 0 0 PRODUCTION 2.08 2022-03-27
xcvc1902 vsva2197 2MP test_versal_vsl_2MP_25 25 1 1 0 1 0 1 rx_core_clk_0=391 s_axi_aclk_0=100 tx_core_clk_0=391 10277 18195 0 0 0 PRODUCTION 2.08 2022-03-27

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
LINE_RATE
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
GT_LOCATION
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV test_usplus_1LV_10 10 1 1 0 1 0 1 rx_core_clk_0=156 s_axi_aclk_0=100 tx_core_clk_0=156 9749 16648 0 0 0 PRODUCTION 1.29 08-03-2020
xczu11eg ffvc1760 1L test_usplus_1L_25 25 1 1 0 1 0 1 rx_core_clk_0=391 s_axi_aclk_0=100 tx_core_clk_0=391 9803 16660 0 0 0 PRODUCTION 1.29 08-03-2020

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