Debugging Techniques

When debugging SDSoC™ applications, you can use the same methods and techniques as applications used for debugging standard C/C++. Most SDSoC applications consist of specific functions tagged for hardware acceleration and surrounded by standard C/C++ code.

When debugging an SDSoC application with a board attached to the debug Host machine, you can use the Assistant view and right-click the Debug[Hardware] > Debug > Launch on Hardware option to begin a debug session. You can also set the options through the Assistant by selecting Debug[Hardware] > Debug > Debug Configurations.

Note: As the debug environment is initialized, Xilinx recommends that users switch to the Debug perspective when prompted by the SDx™ IDE.

The debug perspective view provides the ability to debug the standard C/C++ portions of the application, by single-stepping code, setting and removing breakpoints, displaying variables, dumping registers, viewing memory, and controlling the code flow with run until and jump to type debugging directives. Inputs and outputs can be observed pre- and post- function call to determine correct behavior.

You can determine if a hardware accelerated application meets its real-time requirements by placing debug statements to start and stop a counter just before and just after a hardware accelerated function. The SDx environment provides the sds_clock_counter() function which is typically used to calculate the elapsed time for a hardware accelerated function.

You can also perform debugging without a target board connected to the debug host by building the SDx project for emulation. During emulation, you can control and observe the software and data just as before through the debug perspective view, but you can also view the hardware accelerated functions through a Vivado® simulator waveform viewer. You can observe accelerator signaling for conditions such as Accelerator start, Accelerator done, and monitor data buses for inputs and outputs. Building a project for emulation also avoids a possibly long Vivado implementation step to generate an FPGA bitstream.

See the SDSoC Environment Debugging Guide for information on using the interactive debuggers in the SDx IDE.