Exporting the RTL Design

The final step in the Vitis HLS design flow is to package and export the RTL output. Click the Export RTL toolbar button or click Solution > Export RTL to open the Export RTL dialog box shown in the following figure.

Figure 1: Export RTL Dialog box

The final step in the Vitis HLS flow is to export the RTL design in a form that can be used by other tools in the Xilinx design flow. The RTL design can be packaged into the following output formats:

Table 1. RTL Export Selections
Format Selection Subfolder Comments
Vivado IP (.zip) solution/impl/export.zip

The IP is exported as a ZIP file that can be added to the Vivado IP catalog.

The impl/ip folder also contains the contents of the unzipped IP.

Vitis Kernel (.xo) solution/impl/export.xo

The .xo output can be used for linking by the Vitis compiler in the application acceleration development flow.

You can link the Vitis kernel with other kernels, and the target accelerator card, to build the xclbin file for your accelerated application.

Synthesized Checkpoint (.dcp) solution/impl/ip

This option creates Vivado checkpoint files which can be added directly into a design in the Vivado Design Suite.

This option requires RTL synthesis to be performed. When this option is selected, the flow option with setting syn is automatically selected.

The output includes an HDL wrapper you can use to instantiate the IP into a higher level design.

Vivado IP for System Generator solution/impl/ip

This option creates IP for use with the Vivado edition of System Generator for DSP.

TIP: When Vitis HLS reports the results of the high-level synthesis, it provides an estimate of the results with projected clock frequencies and resource utilization (LUTs, DSPs, BRAMs...). These results are merely estimates because Vitis HLS cannot know what optimizations or routing delays will be, and therefore does not know the actual area and timing values. Choosing to run Vivado synthesis or implementation provides greater accuracy of the final IP, and also makes those results available in other parts of the design flow.

Finally, you can also specify the output location to write the export file to. If the location is not specified, the default location is the solution/impl/ folder of the project.

Configuring the Vivado IP

When you select the Vivado IP format on the Export RTL dialog box, you also have the option of Configuring the IP. Selecting the Configuration button opens the IP Identification dialog box, as shown below, letting you specify information that can help identify the specific IP in the exported RTL.

Figure 2: IP Identification Dialog Box

The Configuration information is used to differentiate between multiple instances of the same design when the design is loaded into the Vivado IP Catalog. For example, if an implementation is packaged for the IP Catalog, and then a new solution is created and packaged as IP, the new solution by default has the same name and configuration information. If the new solution is also added to the IP Catalog, the IP Catalog will identify it as an updated version of the same IP and the last version added to the IP Catalog will be used.

The Configuration options, and their default values are listed below:
  • Vendor: xilinx.com
  • Library: hls
  • Version: 1.0
  • Description: An IP generated by Vitis HLS
  • Display Name: This field is left blank by default
  • Taxonomy: This field is left blank by default
TIP: The default values specified above are applied if no other value is provided.

After the IP packaging process is complete, the.zip file archive in the solution/impl folder can be imported into the Vivado IP catalog and used in any design.

Software Driver Files

For designs that include AXI4-Lite slave interfaces, a set of software driver files is created during the export process. These C driver files can be included in a Vitis embedded software development project, and used to access the AXI4-Lite slave port.

The software driver files are written to directory solution/impl/ip/drivers and are included in the packaged IP export.zip. Refer to AXI4-Lite Interface for details on the C driver files.

Output of RTL Export

Vitis HLS writes to the impl folder of the active solution folder when you run the Export RTL command.

The output files and folders include the following:

  • component.xml: The IP component file that defines the interfaces and architecture.
  • export.zip: The zip archive of the IP and its contents. The zip file can be directly added to the Vivado IP catalog.
  • export.xo: The compiled kernel object for use in the Vitis application acceleration development flow.
  • impl/ip: The IP contents unzipped.
  • impl/ip/example: A folder with a Tcl script used to generate the packaged IP, and a shell script to export the IP.
  • impl/report: The report for the synthesized, or placed and routed IP is written to this folder.
  • impl/verilog: Contains the Verilog format RTL output files.
  • impl/vhdl: Contains the VHDL format RTL output files.
    TIP: If the Vivado synthesis or Vivado synthesis, place, and route options are selected, Vivado synthesis and implementation are performed in the Verilog or VHDL folders. In this case the folder includes a project.xpr file that can be opened in the Vivado Design Suite.
IMPORTANT: Xilinx does not recommend directly using the files in the verilog or vhdl folders for your own RTL synthesis project. Instead, Xilinx recommends using the packaged IP output files. Please carefully read the text that immediately follows this note.

In cases where Vitis HLS uses Xilinx IP in the design, such as with floating point designs, the RTL directory includes a script to create the IP during RTL synthesis. If the files in the verilog or vhdl folders are copied out and used for RTL synthesis, it is your responsibility to correctly use any script files present in those folders. If the package IP is used, this process is performed automatically by the design Xilinx tools. If C/RTL co-simulation has been executed in Vitis HLS, the Vivado project also contains an RTL test bench, and the design can be simulated.

Archiving the Project

After the project has been completed, and the RTL exported, you can archive the Vitis HLS project to an industry-standard Zip file. Select the File > Archive Project menu command to open the Archive Project dialog box as shone below.

Figure 3: Archive Project Dialog Box

The Archive Project dialog box features the following settings:

  • Archive Name: Specifies the name of the archive file to create.
  • Active Solution Only: This is selected by default. Disable this option to include all solutions from the current project.
  • Include Run Results: By default only the source files and constraints will be included in the archive file. Enable this option to also include the results of simulation and synthesis in the archive file.