Resource Utilization for AXI TFT Controller v2.0

Vivado Design Suite Release 2022.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2022.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex-7

Part Information			Configuration Parameters				Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_M_AXI_DATA_WIDTH	C_TFT_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	2	tft_dvi_128	128	1	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	552	1002	0	0	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	tft_dvi_32	32	1	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	539	982	0	0	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	tft_dvi_64	64	1	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	532	1001	0	0	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	tft_vga_128	128	0	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	482	933	0	0	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	tft_vga_32	32	0	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	472	913	0	0	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	tft_vga_64	64	0	m_axi_aclk=100 s_axi_aclk=100 sys_tft_clk=25	463	932	0	0	1	PRODUCTION 1.12 2017-02-17

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