Resource Utilization for Versal ACAP 600G Channelized Multirate Ethernet MAC (DCMAC) v2.3

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Versal ACAP

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
MAC_PORT0_CONFIG_C0
MAC_PORT0_ENABLE_TIME_STAMPING_C0
MAC_PORT1_CONFIG_C0
MAC_PORT2_CONFIG_C0
MAC_PORT3_CONFIG_C0
MAC_PORT4_CONFIG_C0
MAC_PORT5_CONFIG_C0
FEC_SLICE0_CFG_C0
FEC_SLICE1_CFG_C0
FEC_SLICE2_CFG_C0
FEC_SLICE3_CFG_C0
FEC_SLICE4_CFG_C0
FEC_SLICE5_CFG_C0
PORT0_1588v2_Operation_MODE_C0
FAST_SIM_MODE
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvp1802 lsvc4072 2MP dcmac_1x400gaui8_1x200gaui4_pam4 400GAUI-8 N/A N/A N/A 200GAUI-4 N/A RS(544) CL119 N/A N/A N/A RS(544) CL119 N/A 1114 1388 0 0 0 PRODUCTION 2.06 2023-09-14
xcvp1802 lsvc4072 2MP dcmac_1x400gaui8_pam4 400GAUI-8 Disabled Disabled 1 772 963 0 0 0 PRODUCTION 2.06 2023-09-14
xcvp1802 lsvc4072 2MP dcmac_1x400gaui8_pam4_ptp_1step 400GAUI-8 1 Disabled Disabled 1-step 1 771 960 0 0 0 PRODUCTION 2.06 2023-09-14
xcvp1802 lsvc4072 2MP dcmac_1x400gaui8_pam4_ptp_2step 400GAUI-8 1 Disabled Disabled 2-step 1 771 960 0 0 0 PRODUCTION 2.06 2023-09-14
xcvp1802 lsvc4072 2MP dcmac_3x200gaui4_pam4 200GAUI-4 200GAUI-4 200GAUI-4 1123 1403 0 0 0 PRODUCTION 2.06 2023-09-14
xcvp1802 lsvc4072 2MP dcmac_6x100gaui2_pam4 100GAUI-2 100GAUI-2 100GAUI-2 100GAUI-2 100GAUI-2 100GAUI-2 1154 1439 0 0 0 PRODUCTION 2.06 2023-09-14

COPYRIGHT

Copyright 2023 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.