FPD_SMMU_TCU_SECURE Module

FPD_SMMU_TCU_SECURE Module Description

Module Name	FPD_SMMU_TCU_SECURE Module
Modules of this Type	FPD_SMMU_TCU_SECURE
Base Address	0x00FD800000 (FPD_SMMU_TCU_SECURE)
Description	FPD System Memory Management TCU (secure) (aka SMMU500)

FPD_SMMU_TCU_SECURE Module Register Summary

Register Name	Address	Width	Type	Reset Value	Description
SMMU_SCR0	0x0000000000	32	mixedMixed types. See bit-field details.	0x00200001	Provides top-level control of the SMMU.
SMMU_SCR1	0x0000000004	32	mixedMixed types. See bit-field details.	0x02014020	Provides top-level Secure control of the SMMU.
SMMU_SACR	0x0000000010	32	rwNormal read/write	0x04000004	Provides IMPLEMENTATION DEFINED functionality.
SMMU_SIDR0	0x0000000020	32	roRead-only	0xFC013E40	Provides SMMU capability information.
SMMU_SIDR1	0x0000000024	32	roRead-only	0x40000F20	Provides SMMU capability information.
SMMU_SIDR2	0x0000000028	32	roRead-only	0x00005555	Provides SMMU capability information.
SMMU_SIDR7	0x000000003C	32	roRead-only	0x00000024	Provides SMMU capability information.
SMMU_SGFAR_low	0x0000000040	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_sGFSR.
SMMU_SGFAR_high	0x0000000044	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_sGFSR.
SMMU_SGFSR	0x0000000048	32	woWrite-only	0x00000000	Gives the fault status for each of the following possible faults.
SMMU_SGFSRRESTORE	0x000000004C	32	woWrite-only	0x00000000	Restores the state of SMMU_sGFSR, after a reset, for example.
SMMU_SGFSYNR0	0x0000000050	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_sGFSR.
SMMU_SGFSYNR1	0x0000000054	32	rwNormal read/write	0x00000000	Contains fault syndrome information relating to SMMU_sGFSR.
SMMU_STLBIALL	0x0000000060	32	woWrite-only	0x00000000	Invalidates all unlocked Secure entries in the TLB.
SMMU_TLBIVMID	0x0000000064	32	woWrite-only	0x00000000	Invalidates all Non-secure non-Hyp TLB entries having the specified VMID.
SMMU_TLBIALLNSNH	0x0000000068	32	woWrite-only	0x00000000	Invalidates all Non-secure non-Hyp tagged entries in the TLB.
SMMU_STLBGSYNC	0x0000000070	32	woWrite-only	0x00000000	Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.
SMMU_STLBGSTATUS	0x0000000074	32	roRead-only	0x00000000	Gives the status of a TLB maintenance operation.
SMMU_DBGRPTRTBU	0x0000000080	32	rwNormal read/write	0x00000000	Address of TLB entry in a specific TBU.
SMMU_DBGRDATATBU	0x0000000084	32	roRead-only	0x00000000	TLB entry data addressed by TBU debug read pointer.
SMMU_DBGRPTRTCU	0x0000000088	32	rwNormal read/write	0x00000000	Address of an entry from a specific cache in TCU.
SMMU_DBGRDATATCU	0x000000008C	32	roRead-only	0x00000000	Cache entry data addressed by TCU debug read pointer.
SMMU_STLBIVALM_low	0x00000000A0	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVALM_high	0x00000000A4	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVAM_low	0x00000000A8	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVAM_high	0x00000000AC	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIALLM	0x00000000BC	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks in the TLB.
SMMU_NSCR0	0x0000000400	32	mixedMixed types. See bit-field details.	0x00200001	Provides top-level control of the SMMU.
SMMU_NSACR	0x0000000410	32	rwNormal read/write	0x0400001C	Provides IMPLEMENTATION DEFINED functionality.
SMMU_NSGFAR_low	0x0000000440	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_GFSR.
SMMU_NSGFAR_high	0x0000000444	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_GFSR.
SMMU_NSGFSR	0x0000000448	32	woWrite-only	0x00000000	Gives the fault status for each of the following possible faults.
SMMU_NSGFSRRESTORE	0x000000044C	32	woWrite-only	0x00000000	Restores the state of SMMU_GFSR, after a reset, for example.
SMMU_NSGFSYNR0	0x0000000450	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_GFSR.
SMMU_NSGFSYNDR1	0x0000000454	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_GFSR.
SMMU_NSTLBGSYNC	0x0000000470	32	woWrite-only	0x00000000	Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.
SMMU_NSTLBGSTATUS	0x0000000474	32	roRead-only	0x00000000	Gives the status of a TLB maintenance operation.
SMMU_SMR0	0x0000000800	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR1	0x0000000804	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR2	0x0000000808	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR3	0x000000080C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR4	0x0000000810	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR5	0x0000000814	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR6	0x0000000818	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR7	0x000000081C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR8	0x0000000820	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR9	0x0000000824	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR10	0x0000000828	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR11	0x000000082C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR12	0x0000000830	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR13	0x0000000834	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR14	0x0000000838	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR15	0x000000083C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR16	0x0000000840	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR17	0x0000000844	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR18	0x0000000848	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR19	0x000000084C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR20	0x0000000850	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR21	0x0000000854	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR22	0x0000000858	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR23	0x000000085C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR24	0x0000000860	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR25	0x0000000864	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR26	0x0000000868	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR27	0x000000086C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR28	0x0000000870	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR29	0x0000000874	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR30	0x0000000878	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR31	0x000000087C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR32	0x0000000880	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR33	0x0000000884	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR34	0x0000000888	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR35	0x000000088C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR36	0x0000000890	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR37	0x0000000894	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR38	0x0000000898	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR39	0x000000089C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR40	0x00000008A0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR41	0x00000008A4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR42	0x00000008A8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR43	0x00000008AC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR44	0x00000008B0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR45	0x00000008B4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR46	0x00000008B8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR47	0x00000008BC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR48	0x00000008C0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR49	0x00000008C4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR50	0x00000008C8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR51	0x00000008CC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR52	0x00000008D0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR53	0x00000008D4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR54	0x00000008D8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR55	0x00000008DC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR56	0x00000008E0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR57	0x00000008E4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR58	0x00000008E8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR59	0x00000008EC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR60	0x00000008F0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR61	0x00000008F4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR62	0x00000008F8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR63	0x00000008FC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_S2CR0	0x0000000C00	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR1	0x0000000C04	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR2	0x0000000C08	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR3	0x0000000C0C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR4	0x0000000C10	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR5	0x0000000C14	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR6	0x0000000C18	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR7	0x0000000C1C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR8	0x0000000C20	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR9	0x0000000C24	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR10	0x0000000C28	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR11	0x0000000C2C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR12	0x0000000C30	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR13	0x0000000C34	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR14	0x0000000C38	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR15	0x0000000C3C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR16	0x0000000C40	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR17	0x0000000C44	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR18	0x0000000C48	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR19	0x0000000C4C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR20	0x0000000C50	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR21	0x0000000C54	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR22	0x0000000C58	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR23	0x0000000C5C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR24	0x0000000C60	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR25	0x0000000C64	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR26	0x0000000C68	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR27	0x0000000C6C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR28	0x0000000C70	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR29	0x0000000C74	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR30	0x0000000C78	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR31	0x0000000C7C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR32	0x0000000C80	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR33	0x0000000C84	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR34	0x0000000C88	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR35	0x0000000C8C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR36	0x0000000C90	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR37	0x0000000C94	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR38	0x0000000C98	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR39	0x0000000C9C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR40	0x0000000CA0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR41	0x0000000CA4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR42	0x0000000CA8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR43	0x0000000CAC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR44	0x0000000CB0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR45	0x0000000CB4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR46	0x0000000CB8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR47	0x0000000CBC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR48	0x0000000CC0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR49	0x0000000CC4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR50	0x0000000CC8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR51	0x0000000CCC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR52	0x0000000CD0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR53	0x0000000CD4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR54	0x0000000CD8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR55	0x0000000CDC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR56	0x0000000CE0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR57	0x0000000CE4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR58	0x0000000CE8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR59	0x0000000CEC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR60	0x0000000CF0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR61	0x0000000CF4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR62	0x0000000CF8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR63	0x0000000CFC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_PIDR4	0x0000000FD0	32	roRead-only	0x00000004	Peripheral Identificaation register 4
SMMU_PIDR0	0x0000000FE0	32	roRead-only	0x00000081	Peripheral Identificaation register 0
SMMU_PIDR1	0x0000000FE4	32	roRead-only	0x000000B4	Peripheral Identificaation register 1
SMMU_PIDR2	0x0000000FE8	32	roRead-only	0x0000001B	Peripheral Identificaation register 2
SMMU_PIDR3	0x0000000FEC	32	roRead-only	0x00000000	Peripheral Identificaation register 3
SMMU_CIDR0	0x0000000FF0	32	roRead-only	0x0000000D	Component Identification register 0
SMMU_CIDR1	0x0000000FF4	32	roRead-only	0x000000F0	Component Identification register 1
SMMU_CIDR2	0x0000000FF8	32	roRead-only	0x00000005	Component Identification register 2
SMMU_CIDR3	0x0000000FFC	32	roRead-only	0x000000B1	Component Identification register 3
SMMU_CBAR0	0x0000001000	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR1	0x0000001004	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR2	0x0000001008	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR3	0x000000100C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR4	0x0000001010	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR5	0x0000001014	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR6	0x0000001018	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR7	0x000000101C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR8	0x0000001020	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR9	0x0000001024	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR10	0x0000001028	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR11	0x000000102C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR12	0x0000001030	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR13	0x0000001034	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR14	0x0000001038	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR15	0x000000103C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR16	0x0000001040	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR17	0x0000001044	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR18	0x0000001048	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR19	0x000000104C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR20	0x0000001050	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR21	0x0000001054	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR22	0x0000001058	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR23	0x000000105C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR24	0x0000001060	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR25	0x0000001064	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR26	0x0000001068	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR27	0x000000106C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR28	0x0000001070	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR29	0x0000001074	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR30	0x0000001078	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR31	0x000000107C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBFRSYNRA0	0x0000001400	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA1	0x0000001404	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA2	0x0000001408	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA3	0x000000140C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA4	0x0000001410	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA5	0x0000001414	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA6	0x0000001418	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA7	0x000000141C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA8	0x0000001420	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA9	0x0000001424	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA10	0x0000001428	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA11	0x000000142C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA12	0x0000001430	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA13	0x0000001434	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA14	0x0000001438	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA15	0x000000143C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA16	0x0000001440	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA17	0x0000001444	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA18	0x0000001448	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA19	0x000000144C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA20	0x0000001450	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA21	0x0000001454	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA22	0x0000001458	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA23	0x000000145C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA24	0x0000001460	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA25	0x0000001464	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA26	0x0000001468	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA27	0x000000146C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA28	0x0000001470	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA29	0x0000001474	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA30	0x0000001478	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA31	0x000000147C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBA2R0	0x0000001800	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R1	0x0000001804	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R2	0x0000001808	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R3	0x000000180C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R4	0x0000001810	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R5	0x0000001814	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R6	0x0000001818	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R7	0x000000181C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R8	0x0000001820	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R9	0x0000001824	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R10	0x0000001828	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R11	0x000000182C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R12	0x0000001830	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R13	0x0000001834	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R14	0x0000001838	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R15	0x000000183C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R16	0x0000001840	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R17	0x0000001844	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R18	0x0000001848	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R19	0x000000184C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R20	0x0000001850	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R21	0x0000001854	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R22	0x0000001858	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R23	0x000000185C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R24	0x0000001860	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R25	0x0000001864	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R26	0x0000001868	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R27	0x000000186C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R28	0x0000001870	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R29	0x0000001874	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R30	0x0000001878	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R31	0x000000187C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_ITCTRL	0x0000002000	32	rwNormal read/write	0x00000000	This register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode.
SMMU_ITIP	0x0000002004	32	roRead-only	0x00000000	Enables the MMU-500 to read the status of the spniden signal.
SMMU_ITOP_GLBL	0x0000002008	32	mixedMixed types. See bit-field details.	0x00000000	For integration test purposes, allows to enable or disable secure and nonsecure interrupts and write or read most significant bits of TCU MTLB and IPA RAMS.
SMMU_ITOP_PERF_INDEX	0x000000200C	32	woWrite-only	0x00000000	Enables TBU performance interrupts.
SMMU_ITOP_CXT0TO31_RAM0	0x0000002010	32	woWrite-only	0x00000000	Enable the context performance interrupts.
SMMU_TBUQOS0	0x0000002100	32	rwNormal read/write	0x00000000	TBU QoS Values
SMMU_PER	0x0000002200	32	roRead-only	0x00000000	Checks for parity errors in TCU and TBU RAMs.
SMMU_TBU_PWR_STATUS	0x0000002204	32	roRead-only	0x00000000	Provides the power status of TBUs.
PMEVCNTR0	0x0000003000	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR1	0x0000003004	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR2	0x0000003008	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR3	0x000000300C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR4	0x0000003010	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR5	0x0000003014	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR6	0x0000003018	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR7	0x000000301C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR8	0x0000003020	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR9	0x0000003024	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR10	0x0000003028	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR11	0x000000302C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR12	0x0000003030	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR13	0x0000003034	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR14	0x0000003038	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR15	0x000000303C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR16	0x0000003040	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR17	0x0000003044	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR18	0x0000003048	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR19	0x000000304C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR20	0x0000003050	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR21	0x0000003054	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR22	0x0000003058	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR23	0x000000305C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR24	0x0000003060	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR25	0x0000003064	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR26	0x0000003068	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR27	0x000000306C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVTYPER0	0x0000003400	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER1	0x0000003404	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER2	0x0000003408	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER3	0x000000340C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER4	0x0000003410	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER5	0x0000003414	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER6	0x0000003418	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER7	0x000000341C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER8	0x0000003420	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER9	0x0000003424	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER10	0x0000003428	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER11	0x000000342C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER12	0x0000003430	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER13	0x0000003434	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER14	0x0000003438	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER15	0x000000343C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER16	0x0000003440	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER17	0x0000003444	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER18	0x0000003448	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER19	0x000000344C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER20	0x0000003450	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER21	0x0000003454	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER22	0x0000003458	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER23	0x000000345C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER24	0x0000003460	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER25	0x0000003464	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER26	0x0000003468	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER27	0x000000346C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMCGCR0	0x0000003800	32	mixedMixed types. See bit-field details.	0x04000000	Controls Counter group behavior.
PMCGCR1	0x0000003804	32	mixedMixed types. See bit-field details.	0x04010000	Controls Counter group behavior.
PMCGCR2	0x0000003808	32	mixedMixed types. See bit-field details.	0x04020000	Controls Counter group behavior.
PMCGCR3	0x000000380C	32	mixedMixed types. See bit-field details.	0x04030000	Controls Counter group behavior.
PMCGCR4	0x0000003810	32	mixedMixed types. See bit-field details.	0x04040000	Controls Counter group behavior.
PMCGCR5	0x0000003814	32	mixedMixed types. See bit-field details.	0x04050000	Controls Counter group behavior.
PMCGCR6	0x0000003818	32	mixedMixed types. See bit-field details.	0x04060000	Controls Counter group behavior.
PMCGSMR0	0x0000003A00	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR1	0x0000003A04	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR2	0x0000003A08	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR3	0x0000003A0C	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR4	0x0000003A10	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR5	0x0000003A14	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR6	0x0000003A18	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCNTENSET	0x0000003C00	32	woWrite-only	0x00000000	Performance Monitor Counter Enable Set registers are used to enable the event counters PMEVCNTRxx.
PMCNTENCLR	0x0000003C20	32	woWrite-only	0x00000000	Performance Monitor Counter Enable Clear registers are used to disable the event counters PMEVCNTRxx.
PMINTENSET	0x0000003C40	32	woWrite-only	0x00000000	Performance Monitor Interrupt Enable Set registers are used enable the generation of interrupts on overflows of the event counters.
PMINTENCLR	0x0000003C60	32	woWrite-only	0x00000000	Performance Monitor Interrupt Enable Clear registers are used disable the generation of interrupts on overflows of the event counters.
PMOVSCLR	0x0000003C80	32	woWrite-only	0x00000000	Performance Monitor Overflow Status Clear registers are used to clear the overflow status of the event registers.
PMOVSSET	0x0000003CC0	32	woWrite-only	0x00000000	Performance Monitor Overflow Status Set registers contain overflow status for the event counters.
PMCFGR	0x0000003E00	32	roRead-only	0x06011F1B	Performance Monitor Configuration register containss PMU specific configuration data.
PMCR	0x0000003E04	32	mixedMixed types. See bit-field details.	0x00000000	Performance Monitor Configuration register controls the behaviour of the event counters.
PMCEID0	0x0000003E20	32	roRead-only	0x00030303	Performance Monitor Common Event Identification register 0 describes the event classes supported by the SMMU implementation.
PMAUTHSTATUS	0x0000003FB8	32	roRead-only	0x00000080	Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions.
PMDEVTYPE	0x0000003FCC	32	roRead-only	0x00000056	Performance Monitor Device Type register provides the Coresight device type information for the PerformanceMonitors.
SMMU_CB0_SCTLR	0x0000020000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB0_ACTLR	0x0000020004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB0_RESUME	0x0000020008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB0_TCR2	0x0000020010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB0_TTBR0_low	0x0000020020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB0_TTBR0_high	0x0000020024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB0_TTBR1_low	0x0000020028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB0_TTBR1_high	0x000002002C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB0_TCR_lpae	0x0000020030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB0_CONTEXTIDR	0x0000020034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB0_PRRR_MAIR0	0x0000020038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB0_NMRR_MAIR1	0x000002003C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB0_FSR	0x0000020058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB0_FSRRESTORE	0x000002005C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB0_FAR_low	0x0000020060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB0_FAR_high	0x0000020064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB0_FSYNR0	0x0000020068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB0_IPAFAR_low	0x0000020070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB0_IPAFAR_high	0x0000020074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB0_TLBIVA_low	0x0000020600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB0_TLBIVA_high	0x0000020604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB0_TLBIVAA_low	0x0000020608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB0_TLBIVAA_high	0x000002060C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB0_TLBIASID	0x0000020610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB0_TLBIALL	0x0000020618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB0_TLBIVAL_low	0x0000020620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB0_TLBIVAL_high	0x0000020624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB0_TLBIVAAL_low	0x0000020628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB0_TLBIVAAL_high	0x000002062C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB0_TLBIIPAS2_low	0x0000020630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB0_TLBIIPAS2_high	0x0000020634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB0_TLBIIPAS2L_low	0x0000020638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB0_TLBIIPAS2L_high	0x000002063C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB0_TLBSYNC	0x00000207F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB0_TLBSTATUS	0x00000207F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB0_PMEVCNTR0	0x0000020E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR1	0x0000020E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR2	0x0000020E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR3	0x0000020E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVTYPER0	0x0000020E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER1	0x0000020E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER2	0x0000020E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER3	0x0000020E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMCFGR	0x0000020F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB0_PMCR	0x0000020F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB0_PMCEID	0x0000020F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB0_PMCNTENSE	0x0000020F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB0_PMCNTENCLR	0x0000020F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB0_PMCNTENSET	0x0000020F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB0_PMINTENCLR	0x0000020F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB0_PMOVSCLR	0x0000020F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB0_PMOVSSET	0x0000020F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb0_pmauthstatus	0x0000020FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB1_SCTLR	0x0000021000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB1_ACTLR	0x0000021004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB1_RESUME	0x0000021008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB1_TCR2	0x0000021010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB1_TTBR0_low	0x0000021020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB1_TTBR0_high	0x0000021024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB1_TTBR1_low	0x0000021028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB1_TTBR1_high	0x000002102C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB1_TCR_lpae	0x0000021030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB1_CONTEXTIDR	0x0000021034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB1_PRRR_MAIR0	0x0000021038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB1_NMRR_MAIR1	0x000002103C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB1_FSR	0x0000021058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB1_FSRRESTORE	0x000002105C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB1_FAR_low	0x0000021060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB1_FAR_high	0x0000021064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB1_FSYNR0	0x0000021068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB1_IPAFAR_low	0x0000021070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB1_IPAFAR_high	0x0000021074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB1_TLBIVA_low	0x0000021600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB1_TLBIVA_high	0x0000021604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB1_TLBIVAA_low	0x0000021608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB1_TLBIVAA_high	0x000002160C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB1_TLBIASID	0x0000021610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB1_TLBIALL	0x0000021618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB1_TLBIVAL_low	0x0000021620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB1_TLBIVAL_high	0x0000021624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB1_TLBIVAAL_low	0x0000021628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB1_TLBIVAAL_high	0x000002162C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB1_TLBIIPAS2_low	0x0000021630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB1_TLBIIPAS2_high	0x0000021634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB1_TLBIIPAS2L_low	0x0000021638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB1_TLBIIPAS2L_high	0x000002163C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB1_TLBSYNC	0x00000217F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB1_TLBSTATUS	0x00000217F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB1_PMEVCNTR0	0x0000021E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR1	0x0000021E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR2	0x0000021E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR3	0x0000021E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVTYPER0	0x0000021E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER1	0x0000021E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER2	0x0000021E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER3	0x0000021E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMCFGR	0x0000021F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB1_PMCR	0x0000021F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB1_PMCEID	0x0000021F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB1_PMCNTENSE	0x0000021F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB1_PMCNTENCLR	0x0000021F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB1_PMCNTENSET	0x0000021F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB1_PMINTENCLR	0x0000021F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB1_PMOVSCLR	0x0000021F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB1_PMOVSSET	0x0000021F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb1_pmauthstatus	0x0000021FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB2_SCTLR	0x0000022000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB2_ACTLR	0x0000022004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB2_RESUME	0x0000022008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB2_TCR2	0x0000022010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB2_TTBR0_low	0x0000022020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB2_TTBR0_high	0x0000022024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB2_TTBR1_low	0x0000022028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB2_TTBR1_high	0x000002202C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB2_TCR_lpae	0x0000022030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB2_CONTEXTIDR	0x0000022034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB2_PRRR_MAIR0	0x0000022038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB2_NMRR_MAIR1	0x000002203C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB2_FSR	0x0000022058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB2_FSRRESTORE	0x000002205C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB2_FAR_low	0x0000022060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB2_FAR_high	0x0000022064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB2_FSYNR0	0x0000022068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB2_IPAFAR_low	0x0000022070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB2_IPAFAR_high	0x0000022074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB2_TLBIVA_low	0x0000022600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB2_TLBIVA_high	0x0000022604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB2_TLBIVAA_low	0x0000022608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB2_TLBIVAA_high	0x000002260C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB2_TLBIASID	0x0000022610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB2_TLBIALL	0x0000022618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB2_TLBIVAL_low	0x0000022620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB2_TLBIVAL_high	0x0000022624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB2_TLBIVAAL_low	0x0000022628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB2_TLBIVAAL_high	0x000002262C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB2_TLBIIPAS2_low	0x0000022630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB2_TLBIIPAS2_high	0x0000022634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB2_TLBIIPAS2L_low	0x0000022638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB2_TLBIIPAS2L_high	0x000002263C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB2_TLBSYNC	0x00000227F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB2_TLBSTATUS	0x00000227F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB2_PMEVCNTR0	0x0000022E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR1	0x0000022E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR2	0x0000022E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR3	0x0000022E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVTYPER0	0x0000022E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER1	0x0000022E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER2	0x0000022E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER3	0x0000022E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMCFGR	0x0000022F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB2_PMCR	0x0000022F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB2_PMCEID	0x0000022F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB2_PMCNTENSE	0x0000022F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB2_PMCNTENCLR	0x0000022F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB2_PMCNTENSET	0x0000022F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB2_PMINTENCLR	0x0000022F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB2_PMOVSCLR	0x0000022F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB2_PMOVSSET	0x0000022F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb2_pmauthstatus	0x0000022FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB3_SCTLR	0x0000023000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB3_ACTLR	0x0000023004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB3_RESUME	0x0000023008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB3_TCR2	0x0000023010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB3_TTBR0_low	0x0000023020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB3_TTBR0_high	0x0000023024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB3_TTBR1_low	0x0000023028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB3_TTBR1_high	0x000002302C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB3_TCR_lpae	0x0000023030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB3_CONTEXTIDR	0x0000023034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB3_PRRR_MAIR0	0x0000023038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB3_NMRR_MAIR1	0x000002303C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB3_FSR	0x0000023058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB3_FSRRESTORE	0x000002305C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB3_FAR_low	0x0000023060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB3_FAR_high	0x0000023064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB3_FSYNR0	0x0000023068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB3_IPAFAR_low	0x0000023070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB3_IPAFAR_high	0x0000023074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB3_TLBIVA_low	0x0000023600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB3_TLBIVA_high	0x0000023604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB3_TLBIVAA_low	0x0000023608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB3_TLBIVAA_high	0x000002360C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB3_TLBIASID	0x0000023610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB3_TLBIALL	0x0000023618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB3_TLBIVAL_low	0x0000023620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB3_TLBIVAL_high	0x0000023624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB3_TLBIVAAL_low	0x0000023628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB3_TLBIVAAL_high	0x000002362C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB3_TLBIIPAS2_low	0x0000023630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB3_TLBIIPAS2_high	0x0000023634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB3_TLBIIPAS2L_low	0x0000023638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB3_TLBIIPAS2L_high	0x000002363C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB3_TLBSYNC	0x00000237F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB3_TLBSTATUS	0x00000237F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB3_PMEVCNTR0	0x0000023E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR1	0x0000023E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR2	0x0000023E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR3	0x0000023E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVTYPER0	0x0000023E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER1	0x0000023E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER2	0x0000023E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER3	0x0000023E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMCFGR	0x0000023F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB3_PMCR	0x0000023F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB3_PMCEID	0x0000023F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB3_PMCNTENSE	0x0000023F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB3_PMCNTENCLR	0x0000023F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB3_PMCNTENSET	0x0000023F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB3_PMINTENCLR	0x0000023F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB3_PMOVSCLR	0x0000023F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB3_PMOVSSET	0x0000023F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb3_pmauthstatus	0x0000023FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB4_SCTLR	0x0000024000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB4_ACTLR	0x0000024004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB4_RESUME	0x0000024008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB4_TCR2	0x0000024010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB4_TTBR0_low	0x0000024020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB4_TTBR0_high	0x0000024024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB4_TTBR1_low	0x0000024028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB4_TTBR1_high	0x000002402C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB4_TCR_lpae	0x0000024030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB4_CONTEXTIDR	0x0000024034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB4_PRRR_MAIR0	0x0000024038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB4_NMRR_MAIR1	0x000002403C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB4_FSR	0x0000024058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB4_FSRRESTORE	0x000002405C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB4_FAR_low	0x0000024060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB4_FAR_high	0x0000024064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB4_FSYNR0	0x0000024068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB4_IPAFAR_low	0x0000024070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB4_IPAFAR_high	0x0000024074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB4_TLBIVA_low	0x0000024600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB4_TLBIVA_high	0x0000024604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB4_TLBIVAA_low	0x0000024608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB4_TLBIVAA_high	0x000002460C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB4_TLBIASID	0x0000024610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB4_TLBIALL	0x0000024618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB4_TLBIVAL_low	0x0000024620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB4_TLBIVAL_high	0x0000024624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB4_TLBIVAAL_low	0x0000024628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB4_TLBIVAAL_high	0x000002462C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB4_TLBIIPAS2_low	0x0000024630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB4_TLBIIPAS2_high	0x0000024634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB4_TLBIIPAS2L_low	0x0000024638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB4_TLBIIPAS2L_high	0x000002463C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB4_TLBSYNC	0x00000247F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB4_TLBSTATUS	0x00000247F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB4_PMEVCNTR0	0x0000024E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR1	0x0000024E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR2	0x0000024E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR3	0x0000024E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVTYPER0	0x0000024E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER1	0x0000024E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER2	0x0000024E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER3	0x0000024E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMCFGR	0x0000024F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB4_PMCR	0x0000024F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB4_PMCEID	0x0000024F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB4_PMCNTENSE	0x0000024F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB4_PMCNTENCLR	0x0000024F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB4_PMCNTENSET	0x0000024F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB4_PMINTENCLR	0x0000024F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB4_PMOVSCLR	0x0000024F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB4_PMOVSSET	0x0000024F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb4_pmauthstatus	0x0000024FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB5_SCTLR	0x0000025000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB5_ACTLR	0x0000025004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB5_RESUME	0x0000025008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB5_TCR2	0x0000025010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB5_TTBR0_low	0x0000025020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB5_TTBR0_high	0x0000025024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB5_TTBR1_low	0x0000025028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB5_TTBR1_high	0x000002502C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB5_TCR_lpae	0x0000025030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB5_CONTEXTIDR	0x0000025034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB5_PRRR_MAIR0	0x0000025038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB5_NMRR_MAIR1	0x000002503C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB5_FSR	0x0000025058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB5_FSRRESTORE	0x000002505C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB5_FAR_low	0x0000025060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB5_FAR_high	0x0000025064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB5_FSYNR0	0x0000025068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB5_IPAFAR_low	0x0000025070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB5_IPAFAR_high	0x0000025074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB5_TLBIVA_low	0x0000025600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB5_TLBIVA_high	0x0000025604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB5_TLBIVAA_low	0x0000025608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB5_TLBIVAA_high	0x000002560C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB5_TLBIASID	0x0000025610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB5_TLBIALL	0x0000025618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB5_TLBIVAL_low	0x0000025620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB5_TLBIVAL_high	0x0000025624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB5_TLBIVAAL_low	0x0000025628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB5_TLBIVAAL_high	0x000002562C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB5_TLBIIPAS2_low	0x0000025630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB5_TLBIIPAS2_high	0x0000025634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB5_TLBIIPAS2L_low	0x0000025638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB5_TLBIIPAS2L_high	0x000002563C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB5_TLBSYNC	0x00000257F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB5_TLBSTATUS	0x00000257F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB5_PMEVCNTR0	0x0000025E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR1	0x0000025E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR2	0x0000025E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR3	0x0000025E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVTYPER0	0x0000025E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER1	0x0000025E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER2	0x0000025E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER3	0x0000025E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMCFGR	0x0000025F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB5_PMCR	0x0000025F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB5_PMCEID	0x0000025F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB5_PMCNTENSE	0x0000025F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB5_PMCNTENCLR	0x0000025F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB5_PMCNTENSET	0x0000025F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB5_PMINTENCLR	0x0000025F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB5_PMOVSCLR	0x0000025F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB5_PMOVSSET	0x0000025F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb5_pmauthstatus	0x0000025FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB6_SCTLR	0x0000026000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB6_ACTLR	0x0000026004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB6_RESUME	0x0000026008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB6_TCR2	0x0000026010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB6_TTBR0_low	0x0000026020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB6_TTBR0_high	0x0000026024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB6_TTBR1_low	0x0000026028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB6_TTBR1_high	0x000002602C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB6_TCR_lpae	0x0000026030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB6_CONTEXTIDR	0x0000026034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB6_PRRR_MAIR0	0x0000026038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB6_NMRR_MAIR1	0x000002603C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB6_FSR	0x0000026058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB6_FSRRESTORE	0x000002605C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB6_FAR_low	0x0000026060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB6_FAR_high	0x0000026064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB6_FSYNR0	0x0000026068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB6_IPAFAR_low	0x0000026070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB6_IPAFAR_high	0x0000026074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB6_TLBIVA_low	0x0000026600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB6_TLBIVA_high	0x0000026604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB6_TLBIVAA_low	0x0000026608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB6_TLBIVAA_high	0x000002660C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB6_TLBIASID	0x0000026610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB6_TLBIALL	0x0000026618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB6_TLBIVAL_low	0x0000026620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB6_TLBIVAL_high	0x0000026624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB6_TLBIVAAL_low	0x0000026628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB6_TLBIVAAL_high	0x000002662C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB6_TLBIIPAS2_low	0x0000026630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB6_TLBIIPAS2_high	0x0000026634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB6_TLBIIPAS2L_low	0x0000026638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB6_TLBIIPAS2L_high	0x000002663C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB6_TLBSYNC	0x00000267F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB6_TLBSTATUS	0x00000267F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB6_PMEVCNTR0	0x0000026E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR1	0x0000026E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR2	0x0000026E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR3	0x0000026E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVTYPER0	0x0000026E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER1	0x0000026E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER2	0x0000026E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER3	0x0000026E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMCFGR	0x0000026F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB6_PMCR	0x0000026F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB6_PMCEID	0x0000026F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB6_PMCNTENSE	0x0000026F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB6_PMCNTENCLR	0x0000026F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB6_PMCNTENSET	0x0000026F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB6_PMINTENCLR	0x0000026F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB6_PMOVSCLR	0x0000026F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB6_PMOVSSET	0x0000026F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb6_pmauthstatus	0x0000026FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB7_SCTLR	0x0000027000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB7_ACTLR	0x0000027004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB7_RESUME	0x0000027008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB7_TCR2	0x0000027010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB7_TTBR0_low	0x0000027020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB7_TTBR0_high	0x0000027024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB7_TTBR1_low	0x0000027028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB7_TTBR1_high	0x000002702C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB7_TCR_lpae	0x0000027030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB7_CONTEXTIDR	0x0000027034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB7_PRRR_MAIR0	0x0000027038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB7_NMRR_MAIR1	0x000002703C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB7_FSR	0x0000027058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB7_FSRRESTORE	0x000002705C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB7_FAR_low	0x0000027060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB7_FAR_high	0x0000027064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB7_FSYNR0	0x0000027068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB7_IPAFAR_low	0x0000027070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB7_IPAFAR_high	0x0000027074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB7_TLBIVA_low	0x0000027600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB7_TLBIVA_high	0x0000027604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB7_TLBIVAA_low	0x0000027608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB7_TLBIVAA_high	0x000002760C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB7_TLBIASID	0x0000027610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB7_TLBIALL	0x0000027618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB7_TLBIVAL_low	0x0000027620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB7_TLBIVAL_high	0x0000027624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB7_TLBIVAAL_low	0x0000027628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB7_TLBIVAAL_high	0x000002762C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB7_TLBIIPAS2_low	0x0000027630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB7_TLBIIPAS2_high	0x0000027634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB7_TLBIIPAS2L_low	0x0000027638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB7_TLBIIPAS2L_high	0x000002763C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB7_TLBSYNC	0x00000277F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB7_TLBSTATUS	0x00000277F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB7_PMEVCNTR0	0x0000027E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR1	0x0000027E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR2	0x0000027E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR3	0x0000027E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVTYPER0	0x0000027E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER1	0x0000027E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER2	0x0000027E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER3	0x0000027E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMCFGR	0x0000027F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB7_PMCR	0x0000027F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB7_PMCEID	0x0000027F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB7_PMCNTENSE	0x0000027F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB7_PMCNTENCLR	0x0000027F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB7_PMCNTENSET	0x0000027F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB7_PMINTENCLR	0x0000027F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB7_PMOVSCLR	0x0000027F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB7_PMOVSSET	0x0000027F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb7_pmauthstatus	0x0000027FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB8_SCTLR	0x0000028000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB8_ACTLR	0x0000028004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB8_RESUME	0x0000028008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB8_TCR2	0x0000028010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB8_TTBR0_low	0x0000028020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB8_TTBR0_high	0x0000028024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB8_TTBR1_low	0x0000028028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB8_TTBR1_high	0x000002802C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB8_TCR_lpae	0x0000028030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB8_CONTEXTIDR	0x0000028034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB8_PRRR_MAIR0	0x0000028038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB8_NMRR_MAIR1	0x000002803C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB8_FSR	0x0000028058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB8_FSRRESTORE	0x000002805C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB8_FAR_low	0x0000028060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB8_FAR_high	0x0000028064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB8_FSYNR0	0x0000028068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB8_IPAFAR_low	0x0000028070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB8_IPAFAR_high	0x0000028074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB8_TLBIVA_low	0x0000028600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB8_TLBIVA_high	0x0000028604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB8_TLBIVAA_low	0x0000028608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB8_TLBIVAA_high	0x000002860C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB8_TLBIASID	0x0000028610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB8_TLBIALL	0x0000028618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB8_TLBIVAL_low	0x0000028620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB8_TLBIVAL_high	0x0000028624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB8_TLBIVAAL_low	0x0000028628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB8_TLBIVAAL_high	0x000002862C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB8_TLBIIPAS2_low	0x0000028630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB8_TLBIIPAS2_high	0x0000028634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB8_TLBIIPAS2L_low	0x0000028638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB8_TLBIIPAS2L_high	0x000002863C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB8_TLBSYNC	0x00000287F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB8_TLBSTATUS	0x00000287F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB8_PMEVCNTR0	0x0000028E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR1	0x0000028E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR2	0x0000028E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR3	0x0000028E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVTYPER0	0x0000028E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER1	0x0000028E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER2	0x0000028E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER3	0x0000028E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMCFGR	0x0000028F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB8_PMCR	0x0000028F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB8_PMCEID	0x0000028F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB8_PMCNTENSE	0x0000028F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB8_PMCNTENCLR	0x0000028F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB8_PMCNTENSET	0x0000028F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB8_PMINTENCLR	0x0000028F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB8_PMOVSCLR	0x0000028F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB8_PMOVSSET	0x0000028F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb8_pmauthstatus	0x0000028FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB9_SCTLR	0x0000029000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB9_ACTLR	0x0000029004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB9_RESUME	0x0000029008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB9_TCR2	0x0000029010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB9_TTBR0_low	0x0000029020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB9_TTBR0_high	0x0000029024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB9_TTBR1_low	0x0000029028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB9_TTBR1_high	0x000002902C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB9_TCR_lpae	0x0000029030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB9_CONTEXTIDR	0x0000029034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB9_PRRR_MAIR0	0x0000029038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB9_NMRR_MAIR1	0x000002903C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB9_FSR	0x0000029058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB9_FSRRESTORE	0x000002905C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB9_FAR_low	0x0000029060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB9_FAR_high	0x0000029064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB9_FSYNR0	0x0000029068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB9_IPAFAR_low	0x0000029070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB9_IPAFAR_high	0x0000029074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB9_TLBIVA_low	0x0000029600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB9_TLBIVA_high	0x0000029604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB9_TLBIVAA_low	0x0000029608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB9_TLBIVAA_high	0x000002960C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB9_TLBIASID	0x0000029610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB9_TLBIALL	0x0000029618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB9_TLBIVAL_low	0x0000029620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB9_TLBIVAL_high	0x0000029624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB9_TLBIVAAL_low	0x0000029628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB9_TLBIVAAL_high	0x000002962C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB9_TLBIIPAS2_low	0x0000029630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB9_TLBIIPAS2_high	0x0000029634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB9_TLBIIPAS2L_low	0x0000029638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB9_TLBIIPAS2L_high	0x000002963C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB9_TLBSYNC	0x00000297F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB9_TLBSTATUS	0x00000297F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB9_PMEVCNTR0	0x0000029E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR1	0x0000029E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR2	0x0000029E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR3	0x0000029E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVTYPER0	0x0000029E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER1	0x0000029E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER2	0x0000029E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER3	0x0000029E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMCFGR	0x0000029F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB9_PMCR	0x0000029F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB9_PMCEID	0x0000029F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB9_PMCNTENSE	0x0000029F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB9_PMCNTENCLR	0x0000029F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB9_PMCNTENSET	0x0000029F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB9_PMINTENCLR	0x0000029F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB9_PMOVSCLR	0x0000029F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB9_PMOVSSET	0x0000029F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb9_pmauthstatus	0x0000029FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB10_SCTLR	0x000002A000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB10_ACTLR	0x000002A004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB10_RESUME	0x000002A008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB10_TCR2	0x000002A010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB10_TTBR0_low	0x000002A020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB10_TTBR0_high	0x000002A024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB10_TTBR1_low	0x000002A028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB10_TTBR1_high	0x000002A02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB10_TCR_lpae	0x000002A030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB10_CONTEXTIDR	0x000002A034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB10_PRRR_MAIR0	0x000002A038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB10_NMRR_MAIR1	0x000002A03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB10_FSR	0x000002A058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB10_FSRRESTORE	0x000002A05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB10_FAR_low	0x000002A060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB10_FAR_high	0x000002A064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB10_FSYNR0	0x000002A068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB10_IPAFAR_low	0x000002A070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB10_IPAFAR_high	0x000002A074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB10_TLBIVA_low	0x000002A600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB10_TLBIVA_high	0x000002A604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB10_TLBIVAA_low	0x000002A608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB10_TLBIVAA_high	0x000002A60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB10_TLBIASID	0x000002A610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB10_TLBIALL	0x000002A618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB10_TLBIVAL_low	0x000002A620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB10_TLBIVAL_high	0x000002A624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB10_TLBIVAAL_low	0x000002A628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB10_TLBIVAAL_high	0x000002A62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB10_TLBIIPAS2_low	0x000002A630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB10_TLBIIPAS2_high	0x000002A634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB10_TLBIIPAS2L_low	0x000002A638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB10_TLBIIPAS2L_high	0x000002A63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB10_TLBSYNC	0x000002A7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB10_TLBSTATUS	0x000002A7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB10_PMEVCNTR0	0x000002AE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR1	0x000002AE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR2	0x000002AE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR3	0x000002AE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVTYPER0	0x000002AE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER1	0x000002AE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER2	0x000002AE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER3	0x000002AE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMCFGR	0x000002AF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB10_PMCR	0x000002AF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB10_PMCEID	0x000002AF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB10_PMCNTENSE	0x000002AF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB10_PMCNTENCLR	0x000002AF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB10_PMCNTENSET	0x000002AF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB10_PMINTENCLR	0x000002AF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB10_PMOVSCLR	0x000002AF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB10_PMOVSSET	0x000002AF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb10_pmauthstatus	0x000002AFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB11_SCTLR	0x000002B000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB11_ACTLR	0x000002B004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB11_RESUME	0x000002B008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB11_TCR2	0x000002B010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB11_TTBR0_low	0x000002B020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB11_TTBR0_high	0x000002B024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB11_TTBR1_low	0x000002B028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB11_TTBR1_high	0x000002B02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB11_TCR_lpae	0x000002B030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB11_CONTEXTIDR	0x000002B034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB11_PRRR_MAIR0	0x000002B038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB11_NMRR_MAIR1	0x000002B03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB11_FSR	0x000002B058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB11_FSRRESTORE	0x000002B05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB11_FAR_low	0x000002B060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB11_FAR_high	0x000002B064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB11_FSYNR0	0x000002B068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB11_IPAFAR_low	0x000002B070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB11_IPAFAR_high	0x000002B074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB11_TLBIVA_low	0x000002B600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB11_TLBIVA_high	0x000002B604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB11_TLBIVAA_low	0x000002B608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB11_TLBIVAA_high	0x000002B60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB11_TLBIASID	0x000002B610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB11_TLBIALL	0x000002B618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB11_TLBIVAL_low	0x000002B620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB11_TLBIVAL_high	0x000002B624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB11_TLBIVAAL_low	0x000002B628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB11_TLBIVAAL_high	0x000002B62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB11_TLBIIPAS2_low	0x000002B630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB11_TLBIIPAS2_high	0x000002B634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB11_TLBIIPAS2L_low	0x000002B638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB11_TLBIIPAS2L_high	0x000002B63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB11_TLBSYNC	0x000002B7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB11_TLBSTATUS	0x000002B7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB11_PMEVCNTR0	0x000002BE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR1	0x000002BE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR2	0x000002BE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR3	0x000002BE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVTYPER0	0x000002BE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER1	0x000002BE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER2	0x000002BE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER3	0x000002BE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMCFGR	0x000002BF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB11_PMCR	0x000002BF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB11_PMCEID	0x000002BF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB11_PMCNTENSE	0x000002BF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB11_PMCNTENCLR	0x000002BF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB11_PMCNTENSET	0x000002BF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB11_PMINTENCLR	0x000002BF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB11_PMOVSCLR	0x000002BF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB11_PMOVSSET	0x000002BF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb11_pmauthstatus	0x000002BFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB12_SCTLR	0x000002C000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB12_ACTLR	0x000002C004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB12_RESUME	0x000002C008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB12_TCR2	0x000002C010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB12_TTBR0_low	0x000002C020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB12_TTBR0_high	0x000002C024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB12_TTBR1_low	0x000002C028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB12_TTBR1_high	0x000002C02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB12_TCR_lpae	0x000002C030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB12_CONTEXTIDR	0x000002C034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB12_PRRR_MAIR0	0x000002C038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB12_NMRR_MAIR1	0x000002C03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB12_FSR	0x000002C058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB12_FSRRESTORE	0x000002C05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB12_FAR_low	0x000002C060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB12_FAR_high	0x000002C064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB12_FSYNR0	0x000002C068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB12_IPAFAR_low	0x000002C070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB12_IPAFAR_high	0x000002C074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB12_TLBIVA_low	0x000002C600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB12_TLBIVA_high	0x000002C604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB12_TLBIVAA_low	0x000002C608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB12_TLBIVAA_high	0x000002C60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB12_TLBIASID	0x000002C610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB12_TLBIALL	0x000002C618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB12_TLBIVAL_low	0x000002C620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB12_TLBIVAL_high	0x000002C624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB12_TLBIVAAL_low	0x000002C628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB12_TLBIVAAL_high	0x000002C62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB12_TLBIIPAS2_low	0x000002C630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB12_TLBIIPAS2_high	0x000002C634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB12_TLBIIPAS2L_low	0x000002C638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB12_TLBIIPAS2L_high	0x000002C63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB12_TLBSYNC	0x000002C7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB12_TLBSTATUS	0x000002C7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB12_PMEVCNTR0	0x000002CE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR1	0x000002CE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR2	0x000002CE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR3	0x000002CE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVTYPER0	0x000002CE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER1	0x000002CE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER2	0x000002CE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER3	0x000002CE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMCFGR	0x000002CF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB12_PMCR	0x000002CF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB12_PMCEID	0x000002CF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB12_PMCNTENSE	0x000002CF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB12_PMCNTENCLR	0x000002CF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB12_PMCNTENSET	0x000002CF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB12_PMINTENCLR	0x000002CF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB12_PMOVSCLR	0x000002CF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB12_PMOVSSET	0x000002CF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb12_pmauthstatus	0x000002CFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB13_SCTLR	0x000002D000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB13_ACTLR	0x000002D004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB13_RESUME	0x000002D008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB13_TCR2	0x000002D010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB13_TTBR0_low	0x000002D020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB13_TTBR0_high	0x000002D024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB13_TTBR1_low	0x000002D028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB13_TTBR1_high	0x000002D02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB13_TCR_lpae	0x000002D030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB13_CONTEXTIDR	0x000002D034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB13_PRRR_MAIR0	0x000002D038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB13_NMRR_MAIR1	0x000002D03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB13_FSR	0x000002D058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB13_FSRRESTORE	0x000002D05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB13_FAR_low	0x000002D060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB13_FAR_high	0x000002D064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB13_FSYNR0	0x000002D068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB13_IPAFAR_low	0x000002D070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB13_IPAFAR_high	0x000002D074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB13_TLBIVA_low	0x000002D600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB13_TLBIVA_high	0x000002D604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB13_TLBIVAA_low	0x000002D608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB13_TLBIVAA_high	0x000002D60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB13_TLBIASID	0x000002D610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB13_TLBIALL	0x000002D618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB13_TLBIVAL_low	0x000002D620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB13_TLBIVAL_high	0x000002D624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB13_TLBIVAAL_low	0x000002D628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB13_TLBIVAAL_high	0x000002D62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB13_TLBIIPAS2_low	0x000002D630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB13_TLBIIPAS2_high	0x000002D634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB13_TLBIIPAS2L_low	0x000002D638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB13_TLBIIPAS2L_high	0x000002D63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB13_TLBSYNC	0x000002D7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB13_TLBSTATUS	0x000002D7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB13_PMEVCNTR0	0x000002DE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR1	0x000002DE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR2	0x000002DE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR3	0x000002DE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVTYPER0	0x000002DE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER1	0x000002DE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER2	0x000002DE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER3	0x000002DE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMCFGR	0x000002DF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB13_PMCR	0x000002DF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB13_PMCEID	0x000002DF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB13_PMCNTENSE	0x000002DF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB13_PMCNTENCLR	0x000002DF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB13_PMCNTENSET	0x000002DF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB13_PMINTENCLR	0x000002DF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB13_PMOVSCLR	0x000002DF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB13_PMOVSSET	0x000002DF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb13_pmauthstatus	0x000002DFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB14_SCTLR	0x000002E000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB14_ACTLR	0x000002E004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB14_RESUME	0x000002E008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB14_TCR2	0x000002E010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB14_TTBR0_low	0x000002E020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB14_TTBR0_high	0x000002E024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB14_TTBR1_low	0x000002E028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB14_TTBR1_high	0x000002E02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB14_TCR_lpae	0x000002E030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB14_CONTEXTIDR	0x000002E034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB14_PRRR_MAIR0	0x000002E038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB14_NMRR_MAIR1	0x000002E03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB14_FSR	0x000002E058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB14_FSRRESTORE	0x000002E05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB14_FAR_low	0x000002E060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB14_FAR_high	0x000002E064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB14_FSYNR0	0x000002E068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB14_IPAFAR_low	0x000002E070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB14_IPAFAR_high	0x000002E074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB14_TLBIVA_low	0x000002E600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB14_TLBIVA_high	0x000002E604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB14_TLBIVAA_low	0x000002E608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB14_TLBIVAA_high	0x000002E60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB14_TLBIASID	0x000002E610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB14_TLBIALL	0x000002E618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB14_TLBIVAL_low	0x000002E620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB14_TLBIVAL_high	0x000002E624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB14_TLBIVAAL_low	0x000002E628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB14_TLBIVAAL_high	0x000002E62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB14_TLBIIPAS2_low	0x000002E630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB14_TLBIIPAS2_high	0x000002E634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB14_TLBIIPAS2L_low	0x000002E638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB14_TLBIIPAS2L_high	0x000002E63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB14_TLBSYNC	0x000002E7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB14_TLBSTATUS	0x000002E7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB14_PMEVCNTR0	0x000002EE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR1	0x000002EE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR2	0x000002EE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR3	0x000002EE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVTYPER0	0x000002EE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER1	0x000002EE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER2	0x000002EE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER3	0x000002EE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMCFGR	0x000002EF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB14_PMCR	0x000002EF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB14_PMCEID	0x000002EF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB14_PMCNTENSE	0x000002EF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB14_PMCNTENCLR	0x000002EF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB14_PMCNTENSET	0x000002EF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB14_PMINTENCLR	0x000002EF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB14_PMOVSCLR	0x000002EF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB14_PMOVSSET	0x000002EF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb14_pmauthstatus	0x000002EFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB15_SCTLR	0x000002F000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB15_ACTLR	0x000002F004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB15_RESUME	0x000002F008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB15_TCR2	0x000002F010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB15_TTBR0_low	0x000002F020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB15_TTBR0_high	0x000002F024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB15_TTBR1_low	0x000002F028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB15_TTBR1_high	0x000002F02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB15_TCR_lpae	0x000002F030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB15_CONTEXTIDR	0x000002F034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB15_PRRR_MAIR0	0x000002F038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB15_NMRR_MAIR1	0x000002F03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB15_FSR	0x000002F058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB15_FSRRESTORE	0x000002F05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB15_FAR_low	0x000002F060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB15_FAR_high	0x000002F064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB15_FSYNR0	0x000002F068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB15_IPAFAR_low	0x000002F070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB15_IPAFAR_high	0x000002F074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB15_TLBIVA_low	0x000002F600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB15_TLBIVA_high	0x000002F604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB15_TLBIVAA_low	0x000002F608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB15_TLBIVAA_high	0x000002F60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB15_TLBIASID	0x000002F610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB15_TLBIALL	0x000002F618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB15_TLBIVAL_low	0x000002F620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB15_TLBIVAL_high	0x000002F624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB15_TLBIVAAL_low	0x000002F628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB15_TLBIVAAL_high	0x000002F62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB15_TLBIIPAS2_low	0x000002F630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB15_TLBIIPAS2_high	0x000002F634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB15_TLBIIPAS2L_low	0x000002F638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB15_TLBIIPAS2L_high	0x000002F63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB15_TLBSYNC	0x000002F7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB15_TLBSTATUS	0x000002F7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB15_PMEVCNTR0	0x000002FE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR1	0x000002FE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR2	0x000002FE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR3	0x000002FE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVTYPER0	0x000002FE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER1	0x000002FE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER2	0x000002FE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER3	0x000002FE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMCFGR	0x000002FF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB15_PMCR	0x000002FF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB15_PMCEID	0x000002FF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB15_PMCNTENSE	0x000002FF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB15_PMCNTENCLR	0x000002FF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB15_PMCNTENSET	0x000002FF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB15_PMINTENCLR	0x000002FF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB15_PMOVSCLR	0x000002FF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB15_PMOVSSET	0x000002FF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb15_pmauthstatus	0x000002FFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB16_SCTLR	0x0000030000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB16_ACTLR	0x0000030004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB16_RESUME	0x0000030008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB16_TCR2	0x0000030010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB16_TTBR0_low	0x0000030020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB16_TTBR0_high	0x0000030024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB16_TTBR1_low	0x0000030028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB16_TTBR1_high	0x000003002C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB16_TCR_lpae	0x0000030030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB16_CONTEXTIDR	0x0000030034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB16_PRRR_MAIR0	0x0000030038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB16_NMRR_MAIR1	0x000003003C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB16_FSR	0x0000030058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB16_FSRRESTORE	0x000003005C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB16_FAR_low	0x0000030060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB16_FAR_high	0x0000030064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB16_FSYNR0	0x0000030068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB16_IPAFAR_low	0x0000030070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB16_IPAFAR_high	0x0000030074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB16_TLBIVA_low	0x0000030600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB16_TLBIVA_high	0x0000030604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB16_TLBIVAA_low	0x0000030608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB16_TLBIVAA_high	0x000003060C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB16_TLBIASID	0x0000030610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB16_TLBIALL	0x0000030618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB16_TLBIVAL_low	0x0000030620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB16_TLBIVAL_high	0x0000030624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB16_TLBIVAAL_low	0x0000030628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB16_TLBIVAAL_high	0x000003062C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB16_TLBIIPAS2_low	0x0000030630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB16_TLBIIPAS2_high	0x0000030634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB16_TLBIIPAS2L_low	0x0000030638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB16_TLBIIPAS2L_high	0x000003063C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB16_TLBSYNC	0x00000307F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB16_TLBSTATUS	0x00000307F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB16_PMEVCNTR0	0x0000030E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB16_PMEVCNTR1	0x0000030E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB16_PMEVCNTR2	0x0000030E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB16_PMEVCNTR3	0x0000030E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB16_PMEVTYPER0	0x0000030E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB16_PMEVTYPER1	0x0000030E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB16_PMEVTYPER2	0x0000030E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB16_PMEVTYPER3	0x0000030E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB16_PMCFGR	0x0000030F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB16_PMCR	0x0000030F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB16_PMCEID	0x0000030F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB16_PMCNTENSE	0x0000030F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB16_PMCNTENCLR	0x0000030F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB16_PMCNTENSET	0x0000030F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB16_PMINTENCLR	0x0000030F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB16_PMOVSCLR	0x0000030F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB16_PMOVSSET	0x0000030F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb16_pmauthstatus	0x0000030FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB17_SCTLR	0x0000031000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB17_ACTLR	0x0000031004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB17_RESUME	0x0000031008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB17_TCR2	0x0000031010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB17_TTBR0_low	0x0000031020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB17_TTBR0_high	0x0000031024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB17_TTBR1_low	0x0000031028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB17_TTBR1_high	0x000003102C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB17_TCR_lpae	0x0000031030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB17_CONTEXTIDR	0x0000031034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB17_PRRR_MAIR0	0x0000031038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB17_NMRR_MAIR1	0x000003103C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB17_FSR	0x0000031058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB17_FSRRESTORE	0x000003105C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB17_FAR_low	0x0000031060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB17_FAR_high	0x0000031064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB17_FSYNR0	0x0000031068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB17_IPAFAR_low	0x0000031070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB17_IPAFAR_high	0x0000031074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB17_TLBIVA_low	0x0000031600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB17_TLBIVA_high	0x0000031604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB17_TLBIVAA_low	0x0000031608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB17_TLBIVAA_high	0x000003160C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB17_TLBIASID	0x0000031610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB17_TLBIALL	0x0000031618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB17_TLBIVAL_low	0x0000031620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB17_TLBIVAL_high	0x0000031624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB17_TLBIVAAL_low	0x0000031628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB17_TLBIVAAL_high	0x000003162C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB17_TLBIIPAS2_low	0x0000031630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB17_TLBIIPAS2_high	0x0000031634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB17_TLBIIPAS2L_low	0x0000031638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB17_TLBIIPAS2L_high	0x000003163C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB17_TLBSYNC	0x00000317F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB17_TLBSTATUS	0x00000317F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB17_PMEVCNTR0	0x0000031E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB17_PMEVCNTR1	0x0000031E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB17_PMEVCNTR2	0x0000031E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB17_PMEVCNTR3	0x0000031E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB17_PMEVTYPER0	0x0000031E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB17_PMEVTYPER1	0x0000031E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB17_PMEVTYPER2	0x0000031E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB17_PMEVTYPER3	0x0000031E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB17_PMCFGR	0x0000031F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB17_PMCR	0x0000031F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB17_PMCEID	0x0000031F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB17_PMCNTENSE	0x0000031F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB17_PMCNTENCLR	0x0000031F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB17_PMCNTENSET	0x0000031F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB17_PMINTENCLR	0x0000031F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB17_PMOVSCLR	0x0000031F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB17_PMOVSSET	0x0000031F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb17_pmauthstatus	0x0000031FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB18_SCTLR	0x0000032000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB18_ACTLR	0x0000032004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB18_RESUME	0x0000032008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB18_TCR2	0x0000032010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB18_TTBR0_low	0x0000032020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB18_TTBR0_high	0x0000032024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB18_TTBR1_low	0x0000032028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB18_TTBR1_high	0x000003202C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB18_TCR_lpae	0x0000032030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB18_CONTEXTIDR	0x0000032034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB18_PRRR_MAIR0	0x0000032038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB18_NMRR_MAIR1	0x000003203C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB18_FSR	0x0000032058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB18_FSRRESTORE	0x000003205C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB18_FAR_low	0x0000032060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB18_FAR_high	0x0000032064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB18_FSYNR0	0x0000032068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB18_IPAFAR_low	0x0000032070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB18_IPAFAR_high	0x0000032074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB18_TLBIVA_low	0x0000032600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB18_TLBIVA_high	0x0000032604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB18_TLBIVAA_low	0x0000032608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB18_TLBIVAA_high	0x000003260C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB18_TLBIASID	0x0000032610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB18_TLBIALL	0x0000032618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB18_TLBIVAL_low	0x0000032620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB18_TLBIVAL_high	0x0000032624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB18_TLBIVAAL_low	0x0000032628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB18_TLBIVAAL_high	0x000003262C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB18_TLBIIPAS2_low	0x0000032630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB18_TLBIIPAS2_high	0x0000032634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB18_TLBIIPAS2L_low	0x0000032638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB18_TLBIIPAS2L_high	0x000003263C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB18_TLBSYNC	0x00000327F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB18_TLBSTATUS	0x00000327F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB18_PMEVCNTR0	0x0000032E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB18_PMEVCNTR1	0x0000032E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB18_PMEVCNTR2	0x0000032E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB18_PMEVCNTR3	0x0000032E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB18_PMEVTYPER0	0x0000032E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB18_PMEVTYPER1	0x0000032E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB18_PMEVTYPER2	0x0000032E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB18_PMEVTYPER3	0x0000032E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB18_PMCFGR	0x0000032F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB18_PMCR	0x0000032F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB18_PMCEID	0x0000032F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB18_PMCNTENSE	0x0000032F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB18_PMCNTENCLR	0x0000032F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB18_PMCNTENSET	0x0000032F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB18_PMINTENCLR	0x0000032F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB18_PMOVSCLR	0x0000032F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB18_PMOVSSET	0x0000032F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb18_pmauthstatus	0x0000032FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB19_SCTLR	0x0000033000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB19_ACTLR	0x0000033004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB19_RESUME	0x0000033008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB19_TCR2	0x0000033010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB19_TTBR0_low	0x0000033020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB19_TTBR0_high	0x0000033024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB19_TTBR1_low	0x0000033028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB19_TTBR1_high	0x000003302C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB19_TCR_lpae	0x0000033030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB19_CONTEXTIDR	0x0000033034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB19_PRRR_MAIR0	0x0000033038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB19_NMRR_MAIR1	0x000003303C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB19_FSR	0x0000033058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB19_FSRRESTORE	0x000003305C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB19_FAR_low	0x0000033060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB19_FAR_high	0x0000033064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB19_FSYNR0	0x0000033068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB19_IPAFAR_low	0x0000033070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB19_IPAFAR_high	0x0000033074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB19_TLBIVA_low	0x0000033600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB19_TLBIVA_high	0x0000033604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB19_TLBIVAA_low	0x0000033608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB19_TLBIVAA_high	0x000003360C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB19_TLBIASID	0x0000033610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB19_TLBIALL	0x0000033618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB19_TLBIVAL_low	0x0000033620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB19_TLBIVAL_high	0x0000033624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB19_TLBIVAAL_low	0x0000033628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB19_TLBIVAAL_high	0x000003362C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB19_TLBIIPAS2_low	0x0000033630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB19_TLBIIPAS2_high	0x0000033634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB19_TLBIIPAS2L_low	0x0000033638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB19_TLBIIPAS2L_high	0x000003363C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB19_TLBSYNC	0x00000337F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB19_TLBSTATUS	0x00000337F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB19_PMEVCNTR0	0x0000033E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB19_PMEVCNTR1	0x0000033E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB19_PMEVCNTR2	0x0000033E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB19_PMEVCNTR3	0x0000033E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB19_PMEVTYPER0	0x0000033E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB19_PMEVTYPER1	0x0000033E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB19_PMEVTYPER2	0x0000033E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB19_PMEVTYPER3	0x0000033E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB19_PMCFGR	0x0000033F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB19_PMCR	0x0000033F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB19_PMCEID	0x0000033F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB19_PMCNTENSE	0x0000033F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB19_PMCNTENCLR	0x0000033F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB19_PMCNTENSET	0x0000033F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB19_PMINTENCLR	0x0000033F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB19_PMOVSCLR	0x0000033F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB19_PMOVSSET	0x0000033F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb19_pmauthstatus	0x0000033FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB20_SCTLR	0x0000034000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB20_ACTLR	0x0000034004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB20_RESUME	0x0000034008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB20_TCR2	0x0000034010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB20_TTBR0_low	0x0000034020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB20_TTBR0_high	0x0000034024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB20_TTBR1_low	0x0000034028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB20_TTBR1_high	0x000003402C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB20_TCR_lpae	0x0000034030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB20_CONTEXTIDR	0x0000034034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB20_PRRR_MAIR0	0x0000034038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB20_NMRR_MAIR1	0x000003403C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB20_FSR	0x0000034058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB20_FSRRESTORE	0x000003405C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB20_FAR_low	0x0000034060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB20_FAR_high	0x0000034064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB20_FSYNR0	0x0000034068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB20_IPAFAR_low	0x0000034070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB20_IPAFAR_high	0x0000034074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB20_TLBIVA_low	0x0000034600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB20_TLBIVA_high	0x0000034604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB20_TLBIVAA_low	0x0000034608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB20_TLBIVAA_high	0x000003460C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB20_TLBIASID	0x0000034610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB20_TLBIALL	0x0000034618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB20_TLBIVAL_low	0x0000034620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB20_TLBIVAL_high	0x0000034624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB20_TLBIVAAL_low	0x0000034628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB20_TLBIVAAL_high	0x000003462C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB20_TLBIIPAS2_low	0x0000034630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB20_TLBIIPAS2_high	0x0000034634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB20_TLBIIPAS2L_low	0x0000034638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB20_TLBIIPAS2L_high	0x000003463C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB20_TLBSYNC	0x00000347F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB20_TLBSTATUS	0x00000347F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB20_PMEVCNTR0	0x0000034E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB20_PMEVCNTR1	0x0000034E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB20_PMEVCNTR2	0x0000034E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB20_PMEVCNTR3	0x0000034E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB20_PMEVTYPER0	0x0000034E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB20_PMEVTYPER1	0x0000034E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB20_PMEVTYPER2	0x0000034E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB20_PMEVTYPER3	0x0000034E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB20_PMCFGR	0x0000034F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB20_PMCR	0x0000034F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB20_PMCEID	0x0000034F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB20_PMCNTENSE	0x0000034F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB20_PMCNTENCLR	0x0000034F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB20_PMCNTENSET	0x0000034F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB20_PMINTENCLR	0x0000034F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB20_PMOVSCLR	0x0000034F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB20_PMOVSSET	0x0000034F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb20_pmauthstatus	0x0000034FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB21_SCTLR	0x0000035000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB21_ACTLR	0x0000035004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB21_RESUME	0x0000035008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB21_TCR2	0x0000035010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB21_TTBR0_low	0x0000035020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB21_TTBR0_high	0x0000035024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB21_TTBR1_low	0x0000035028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB21_TTBR1_high	0x000003502C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB21_TCR_lpae	0x0000035030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB21_CONTEXTIDR	0x0000035034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB21_PRRR_MAIR0	0x0000035038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB21_NMRR_MAIR1	0x000003503C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB21_FSR	0x0000035058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB21_FSRRESTORE	0x000003505C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB21_FAR_low	0x0000035060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB21_FAR_high	0x0000035064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB21_FSYNR0	0x0000035068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB21_IPAFAR_low	0x0000035070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB21_IPAFAR_high	0x0000035074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB21_TLBIVA_low	0x0000035600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB21_TLBIVA_high	0x0000035604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB21_TLBIVAA_low	0x0000035608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB21_TLBIVAA_high	0x000003560C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB21_TLBIASID	0x0000035610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB21_TLBIALL	0x0000035618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB21_TLBIVAL_low	0x0000035620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB21_TLBIVAL_high	0x0000035624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB21_TLBIVAAL_low	0x0000035628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB21_TLBIVAAL_high	0x000003562C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB21_TLBIIPAS2_low	0x0000035630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB21_TLBIIPAS2_high	0x0000035634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB21_TLBIIPAS2L_low	0x0000035638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB21_TLBIIPAS2L_high	0x000003563C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB21_TLBSYNC	0x00000357F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB21_TLBSTATUS	0x00000357F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB21_PMEVCNTR0	0x0000035E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB21_PMEVCNTR1	0x0000035E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB21_PMEVCNTR2	0x0000035E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB21_PMEVCNTR3	0x0000035E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB21_PMEVTYPER0	0x0000035E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB21_PMEVTYPER1	0x0000035E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB21_PMEVTYPER2	0x0000035E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB21_PMEVTYPER3	0x0000035E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB21_PMCFGR	0x0000035F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB21_PMCR	0x0000035F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB21_PMCEID	0x0000035F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB21_PMCNTENSE	0x0000035F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB21_PMCNTENCLR	0x0000035F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB21_PMCNTENSET	0x0000035F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB21_PMINTENCLR	0x0000035F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB21_PMOVSCLR	0x0000035F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB21_PMOVSSET	0x0000035F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb21_pmauthstatus	0x0000035FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB22_SCTLR	0x0000036000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB22_ACTLR	0x0000036004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB22_RESUME	0x0000036008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB22_TCR2	0x0000036010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB22_TTBR0_low	0x0000036020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB22_TTBR0_high	0x0000036024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB22_TTBR1_low	0x0000036028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB22_TTBR1_high	0x000003602C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB22_TCR_lpae	0x0000036030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB22_CONTEXTIDR	0x0000036034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB22_PRRR_MAIR0	0x0000036038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB22_NMRR_MAIR1	0x000003603C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB22_FSR	0x0000036058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB22_FSRRESTORE	0x000003605C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB22_FAR_low	0x0000036060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB22_FAR_high	0x0000036064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB22_FSYNR0	0x0000036068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB22_IPAFAR_low	0x0000036070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB22_IPAFAR_high	0x0000036074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB22_TLBIVA_low	0x0000036600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB22_TLBIVA_high	0x0000036604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB22_TLBIVAA_low	0x0000036608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB22_TLBIVAA_high	0x000003660C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB22_TLBIASID	0x0000036610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB22_TLBIALL	0x0000036618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB22_TLBIVAL_low	0x0000036620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB22_TLBIVAL_high	0x0000036624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB22_TLBIVAAL_low	0x0000036628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB22_TLBIVAAL_high	0x000003662C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB22_TLBIIPAS2_low	0x0000036630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB22_TLBIIPAS2_high	0x0000036634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB22_TLBIIPAS2L_low	0x0000036638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB22_TLBIIPAS2L_high	0x000003663C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB22_TLBSYNC	0x00000367F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB22_TLBSTATUS	0x00000367F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB22_PMEVCNTR0	0x0000036E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB22_PMEVCNTR1	0x0000036E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB22_PMEVCNTR2	0x0000036E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB22_PMEVCNTR3	0x0000036E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB22_PMEVTYPER0	0x0000036E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB22_PMEVTYPER1	0x0000036E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB22_PMEVTYPER2	0x0000036E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB22_PMEVTYPER3	0x0000036E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB22_PMCFGR	0x0000036F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB22_PMCR	0x0000036F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB22_PMCEID	0x0000036F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB22_PMCNTENSE	0x0000036F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB22_PMCNTENCLR	0x0000036F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB22_PMCNTENSET	0x0000036F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB22_PMINTENCLR	0x0000036F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB22_PMOVSCLR	0x0000036F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB22_PMOVSSET	0x0000036F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb22_pmauthstatus	0x0000036FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB23_SCTLR	0x0000037000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB23_ACTLR	0x0000037004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB23_RESUME	0x0000037008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB23_TCR2	0x0000037010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB23_TTBR0_low	0x0000037020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB23_TTBR0_high	0x0000037024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB23_TTBR1_low	0x0000037028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB23_TTBR1_high	0x000003702C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB23_TCR_lpae	0x0000037030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB23_CONTEXTIDR	0x0000037034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB23_PRRR_MAIR0	0x0000037038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB23_NMRR_MAIR1	0x000003703C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB23_FSR	0x0000037058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB23_FSRRESTORE	0x000003705C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB23_FAR_low	0x0000037060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB23_FAR_high	0x0000037064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB23_FSYNR0	0x0000037068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB23_IPAFAR_low	0x0000037070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB23_IPAFAR_high	0x0000037074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB23_TLBIVA_low	0x0000037600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB23_TLBIVA_high	0x0000037604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB23_TLBIVAA_low	0x0000037608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB23_TLBIVAA_high	0x000003760C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB23_TLBIASID	0x0000037610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB23_TLBIALL	0x0000037618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB23_TLBIVAL_low	0x0000037620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB23_TLBIVAL_high	0x0000037624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB23_TLBIVAAL_low	0x0000037628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB23_TLBIVAAL_high	0x000003762C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB23_TLBIIPAS2_low	0x0000037630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB23_TLBIIPAS2_high	0x0000037634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB23_TLBIIPAS2L_low	0x0000037638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB23_TLBIIPAS2L_high	0x000003763C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB23_TLBSYNC	0x00000377F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB23_TLBSTATUS	0x00000377F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB23_PMEVCNTR0	0x0000037E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB23_PMEVCNTR1	0x0000037E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB23_PMEVCNTR2	0x0000037E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB23_PMEVCNTR3	0x0000037E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB23_PMEVTYPER0	0x0000037E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB23_PMEVTYPER1	0x0000037E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB23_PMEVTYPER2	0x0000037E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB23_PMEVTYPER3	0x0000037E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB23_PMCFGR	0x0000037F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB23_PMCR	0x0000037F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB23_PMCEID	0x0000037F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB23_PMCNTENSE	0x0000037F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB23_PMCNTENCLR	0x0000037F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB23_PMCNTENSET	0x0000037F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB23_PMINTENCLR	0x0000037F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB23_PMOVSCLR	0x0000037F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB23_PMOVSSET	0x0000037F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb23_pmauthstatus	0x0000037FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB24_SCTLR	0x0000038000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB24_ACTLR	0x0000038004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB24_RESUME	0x0000038008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB24_TCR2	0x0000038010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB24_TTBR0_low	0x0000038020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB24_TTBR0_high	0x0000038024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB24_TTBR1_low	0x0000038028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB24_TTBR1_high	0x000003802C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB24_TCR_lpae	0x0000038030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB24_CONTEXTIDR	0x0000038034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB24_PRRR_MAIR0	0x0000038038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB24_NMRR_MAIR1	0x000003803C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB24_FSR	0x0000038058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB24_FSRRESTORE	0x000003805C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB24_FAR_low	0x0000038060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB24_FAR_high	0x0000038064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB24_FSYNR0	0x0000038068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB24_IPAFAR_low	0x0000038070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB24_IPAFAR_high	0x0000038074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB24_TLBIVA_low	0x0000038600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB24_TLBIVA_high	0x0000038604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB24_TLBIVAA_low	0x0000038608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB24_TLBIVAA_high	0x000003860C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB24_TLBIASID	0x0000038610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB24_TLBIALL	0x0000038618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB24_TLBIVAL_low	0x0000038620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB24_TLBIVAL_high	0x0000038624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB24_TLBIVAAL_low	0x0000038628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB24_TLBIVAAL_high	0x000003862C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB24_TLBIIPAS2_low	0x0000038630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB24_TLBIIPAS2_high	0x0000038634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB24_TLBIIPAS2L_low	0x0000038638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB24_TLBIIPAS2L_high	0x000003863C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB24_TLBSYNC	0x00000387F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB24_TLBSTATUS	0x00000387F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB24_PMEVCNTR0	0x0000038E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB24_PMEVCNTR1	0x0000038E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB24_PMEVCNTR2	0x0000038E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB24_PMEVCNTR3	0x0000038E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB24_PMEVTYPER0	0x0000038E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB24_PMEVTYPER1	0x0000038E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB24_PMEVTYPER2	0x0000038E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB24_PMEVTYPER3	0x0000038E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB24_PMCFGR	0x0000038F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB24_PMCR	0x0000038F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB24_PMCEID	0x0000038F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB24_PMCNTENSE	0x0000038F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB24_PMCNTENCLR	0x0000038F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB24_PMCNTENSET	0x0000038F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB24_PMINTENCLR	0x0000038F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB24_PMOVSCLR	0x0000038F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB24_PMOVSSET	0x0000038F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb24_pmauthstatus	0x0000038FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB25_SCTLR	0x0000039000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB25_ACTLR	0x0000039004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB25_RESUME	0x0000039008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB25_TCR2	0x0000039010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB25_TTBR0_low	0x0000039020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB25_TTBR0_high	0x0000039024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB25_TTBR1_low	0x0000039028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB25_TTBR1_high	0x000003902C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB25_TCR_lpae	0x0000039030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB25_CONTEXTIDR	0x0000039034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB25_PRRR_MAIR0	0x0000039038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB25_NMRR_MAIR1	0x000003903C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB25_FSR	0x0000039058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB25_FSRRESTORE	0x000003905C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB25_FAR_low	0x0000039060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB25_FAR_high	0x0000039064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB25_FSYNR0	0x0000039068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB25_IPAFAR_low	0x0000039070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB25_IPAFAR_high	0x0000039074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB25_TLBIVA_low	0x0000039600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB25_TLBIVA_high	0x0000039604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB25_TLBIVAA_low	0x0000039608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB25_TLBIVAA_high	0x000003960C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB25_TLBIASID	0x0000039610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB25_TLBIALL	0x0000039618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB25_TLBIVAL_low	0x0000039620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB25_TLBIVAL_high	0x0000039624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB25_TLBIVAAL_low	0x0000039628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB25_TLBIVAAL_high	0x000003962C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB25_TLBIIPAS2_low	0x0000039630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB25_TLBIIPAS2_high	0x0000039634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB25_TLBIIPAS2L_low	0x0000039638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB25_TLBIIPAS2L_high	0x000003963C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB25_TLBSYNC	0x00000397F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB25_TLBSTATUS	0x00000397F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB25_PMEVCNTR0	0x0000039E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB25_PMEVCNTR1	0x0000039E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB25_PMEVCNTR2	0x0000039E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB25_PMEVCNTR3	0x0000039E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB25_PMEVTYPER0	0x0000039E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB25_PMEVTYPER1	0x0000039E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB25_PMEVTYPER2	0x0000039E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB25_PMEVTYPER3	0x0000039E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB25_PMCFGR	0x0000039F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB25_PMCR	0x0000039F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB25_PMCEID	0x0000039F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB25_PMCNTENSE	0x0000039F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB25_PMCNTENCLR	0x0000039F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB25_PMCNTENSET	0x0000039F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB25_PMINTENCLR	0x0000039F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB25_PMOVSCLR	0x0000039F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB25_PMOVSSET	0x0000039F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb25_pmauthstatus	0x0000039FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB26_SCTLR	0x000003A000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB26_ACTLR	0x000003A004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB26_RESUME	0x000003A008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB26_TCR2	0x000003A010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB26_TTBR0_low	0x000003A020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB26_TTBR0_high	0x000003A024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB26_TTBR1_low	0x000003A028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB26_TTBR1_high	0x000003A02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB26_TCR_lpae	0x000003A030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB26_CONTEXTIDR	0x000003A034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB26_PRRR_MAIR0	0x000003A038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB26_NMRR_MAIR1	0x000003A03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB26_FSR	0x000003A058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB26_FSRRESTORE	0x000003A05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB26_FAR_low	0x000003A060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB26_FAR_high	0x000003A064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB26_FSYNR0	0x000003A068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB26_IPAFAR_low	0x000003A070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB26_IPAFAR_high	0x000003A074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB26_TLBIVA_low	0x000003A600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB26_TLBIVA_high	0x000003A604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB26_TLBIVAA_low	0x000003A608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB26_TLBIVAA_high	0x000003A60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB26_TLBIASID	0x000003A610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB26_TLBIALL	0x000003A618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB26_TLBIVAL_low	0x000003A620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB26_TLBIVAL_high	0x000003A624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB26_TLBIVAAL_low	0x000003A628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB26_TLBIVAAL_high	0x000003A62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB26_TLBIIPAS2_low	0x000003A630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB26_TLBIIPAS2_high	0x000003A634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB26_TLBIIPAS2L_low	0x000003A638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB26_TLBIIPAS2L_high	0x000003A63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB26_TLBSYNC	0x000003A7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB26_TLBSTATUS	0x000003A7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB26_PMEVCNTR0	0x000003AE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB26_PMEVCNTR1	0x000003AE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB26_PMEVCNTR2	0x000003AE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB26_PMEVCNTR3	0x000003AE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB26_PMEVTYPER0	0x000003AE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB26_PMEVTYPER1	0x000003AE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB26_PMEVTYPER2	0x000003AE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB26_PMEVTYPER3	0x000003AE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB26_PMCFGR	0x000003AF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB26_PMCR	0x000003AF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB26_PMCEID	0x000003AF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB26_PMCNTENSE	0x000003AF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB26_PMCNTENCLR	0x000003AF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB26_PMCNTENSET	0x000003AF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB26_PMINTENCLR	0x000003AF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB26_PMOVSCLR	0x000003AF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB26_PMOVSSET	0x000003AF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb26_pmauthstatus	0x000003AFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB27_SCTLR	0x000003B000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB27_ACTLR	0x000003B004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB27_RESUME	0x000003B008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB27_TCR2	0x000003B010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB27_TTBR0_low	0x000003B020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB27_TTBR0_high	0x000003B024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB27_TTBR1_low	0x000003B028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB27_TTBR1_high	0x000003B02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB27_TCR_lpae	0x000003B030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB27_CONTEXTIDR	0x000003B034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB27_PRRR_MAIR0	0x000003B038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB27_NMRR_MAIR1	0x000003B03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB27_FSR	0x000003B058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB27_FSRRESTORE	0x000003B05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB27_FAR_low	0x000003B060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB27_FAR_high	0x000003B064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB27_FSYNR0	0x000003B068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB27_IPAFAR_low	0x000003B070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB27_IPAFAR_high	0x000003B074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB27_TLBIVA_low	0x000003B600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB27_TLBIVA_high	0x000003B604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB27_TLBIVAA_low	0x000003B608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB27_TLBIVAA_high	0x000003B60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB27_TLBIASID	0x000003B610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB27_TLBIALL	0x000003B618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB27_TLBIVAL_low	0x000003B620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB27_TLBIVAL_high	0x000003B624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB27_TLBIVAAL_low	0x000003B628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB27_TLBIVAAL_high	0x000003B62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB27_TLBIIPAS2_low	0x000003B630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB27_TLBIIPAS2_high	0x000003B634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB27_TLBIIPAS2L_low	0x000003B638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB27_TLBIIPAS2L_high	0x000003B63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB27_TLBSYNC	0x000003B7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB27_TLBSTATUS	0x000003B7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB27_PMEVCNTR0	0x000003BE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB27_PMEVCNTR1	0x000003BE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB27_PMEVCNTR2	0x000003BE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB27_PMEVCNTR3	0x000003BE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB27_PMEVTYPER0	0x000003BE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB27_PMEVTYPER1	0x000003BE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB27_PMEVTYPER2	0x000003BE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB27_PMEVTYPER3	0x000003BE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB27_PMCFGR	0x000003BF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB27_PMCR	0x000003BF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB27_PMCEID	0x000003BF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB27_PMCNTENSE	0x000003BF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB27_PMCNTENCLR	0x000003BF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB27_PMCNTENSET	0x000003BF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB27_PMINTENCLR	0x000003BF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB27_PMOVSCLR	0x000003BF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB27_PMOVSSET	0x000003BF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb27_pmauthstatus	0x000003BFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB28_SCTLR	0x000003C000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB28_ACTLR	0x000003C004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB28_RESUME	0x000003C008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB28_TCR2	0x000003C010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB28_TTBR0_low	0x000003C020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB28_TTBR0_high	0x000003C024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB28_TTBR1_low	0x000003C028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB28_TTBR1_high	0x000003C02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB28_TCR_lpae	0x000003C030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB28_CONTEXTIDR	0x000003C034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB28_PRRR_MAIR0	0x000003C038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB28_NMRR_MAIR1	0x000003C03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB28_FSR	0x000003C058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB28_FSRRESTORE	0x000003C05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB28_FAR_low	0x000003C060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB28_FAR_high	0x000003C064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB28_FSYNR0	0x000003C068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB28_IPAFAR_low	0x000003C070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB28_IPAFAR_high	0x000003C074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB28_TLBIVA_low	0x000003C600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB28_TLBIVA_high	0x000003C604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB28_TLBIVAA_low	0x000003C608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB28_TLBIVAA_high	0x000003C60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB28_TLBIASID	0x000003C610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB28_TLBIALL	0x000003C618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB28_TLBIVAL_low	0x000003C620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB28_TLBIVAL_high	0x000003C624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB28_TLBIVAAL_low	0x000003C628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB28_TLBIVAAL_high	0x000003C62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB28_TLBIIPAS2_low	0x000003C630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB28_TLBIIPAS2_high	0x000003C634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB28_TLBIIPAS2L_low	0x000003C638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB28_TLBIIPAS2L_high	0x000003C63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB28_TLBSYNC	0x000003C7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB28_TLBSTATUS	0x000003C7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB28_PMEVCNTR0	0x000003CE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB28_PMEVCNTR1	0x000003CE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB28_PMEVCNTR2	0x000003CE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB28_PMEVCNTR3	0x000003CE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB28_PMEVTYPER0	0x000003CE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB28_PMEVTYPER1	0x000003CE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB28_PMEVTYPER2	0x000003CE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB28_PMEVTYPER3	0x000003CE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB28_PMCFGR	0x000003CF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB28_PMCR	0x000003CF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB28_PMCEID	0x000003CF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB28_PMCNTENSE	0x000003CF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB28_PMCNTENCLR	0x000003CF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB28_PMCNTENSET	0x000003CF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB28_PMINTENCLR	0x000003CF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB28_PMOVSCLR	0x000003CF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB28_PMOVSSET	0x000003CF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb28_pmauthstatus	0x000003CFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB29_SCTLR	0x000003D000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB29_ACTLR	0x000003D004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB29_RESUME	0x000003D008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB29_TCR2	0x000003D010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB29_TTBR0_low	0x000003D020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB29_TTBR0_high	0x000003D024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB29_TTBR1_low	0x000003D028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB29_TTBR1_high	0x000003D02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB29_TCR_lpae	0x000003D030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB29_CONTEXTIDR	0x000003D034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB29_PRRR_MAIR0	0x000003D038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB29_NMRR_MAIR1	0x000003D03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB29_FSR	0x000003D058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB29_FSRRESTORE	0x000003D05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB29_FAR_low	0x000003D060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB29_FAR_high	0x000003D064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB29_FSYNR0	0x000003D068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB29_IPAFAR_low	0x000003D070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB29_IPAFAR_high	0x000003D074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB29_TLBIVA_low	0x000003D600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB29_TLBIVA_high	0x000003D604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB29_TLBIVAA_low	0x000003D608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB29_TLBIVAA_high	0x000003D60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB29_TLBIASID	0x000003D610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB29_TLBIALL	0x000003D618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB29_TLBIVAL_low	0x000003D620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB29_TLBIVAL_high	0x000003D624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB29_TLBIVAAL_low	0x000003D628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB29_TLBIVAAL_high	0x000003D62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB29_TLBIIPAS2_low	0x000003D630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB29_TLBIIPAS2_high	0x000003D634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB29_TLBIIPAS2L_low	0x000003D638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB29_TLBIIPAS2L_high	0x000003D63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB29_TLBSYNC	0x000003D7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB29_TLBSTATUS	0x000003D7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB29_PMEVCNTR0	0x000003DE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB29_PMEVCNTR1	0x000003DE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB29_PMEVCNTR2	0x000003DE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB29_PMEVCNTR3	0x000003DE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB29_PMEVTYPER0	0x000003DE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB29_PMEVTYPER1	0x000003DE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB29_PMEVTYPER2	0x000003DE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB29_PMEVTYPER3	0x000003DE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB29_PMCFGR	0x000003DF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB29_PMCR	0x000003DF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB29_PMCEID	0x000003DF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB29_PMCNTENSE	0x000003DF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB29_PMCNTENCLR	0x000003DF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB29_PMCNTENSET	0x000003DF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB29_PMINTENCLR	0x000003DF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB29_PMOVSCLR	0x000003DF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB29_PMOVSSET	0x000003DF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb29_pmauthstatus	0x000003DFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB30_SCTLR	0x000003E000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB30_ACTLR	0x000003E004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB30_RESUME	0x000003E008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB30_TCR2	0x000003E010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB30_TTBR0_low	0x000003E020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB30_TTBR0_high	0x000003E024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB30_TTBR1_low	0x000003E028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB30_TTBR1_high	0x000003E02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB30_TCR_lpae	0x000003E030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB30_CONTEXTIDR	0x000003E034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB30_PRRR_MAIR0	0x000003E038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB30_NMRR_MAIR1	0x000003E03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB30_FSR	0x000003E058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB30_FSRRESTORE	0x000003E05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB30_FAR_low	0x000003E060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB30_FAR_high	0x000003E064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB30_FSYNR0	0x000003E068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB30_IPAFAR_low	0x000003E070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB30_IPAFAR_high	0x000003E074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB30_TLBIVA_low	0x000003E600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB30_TLBIVA_high	0x000003E604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB30_TLBIVAA_low	0x000003E608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB30_TLBIVAA_high	0x000003E60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB30_TLBIASID	0x000003E610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB30_TLBIALL	0x000003E618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB30_TLBIVAL_low	0x000003E620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB30_TLBIVAL_high	0x000003E624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB30_TLBIVAAL_low	0x000003E628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB30_TLBIVAAL_high	0x000003E62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB30_TLBIIPAS2_low	0x000003E630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB30_TLBIIPAS2_high	0x000003E634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB30_TLBIIPAS2L_low	0x000003E638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB30_TLBIIPAS2L_high	0x000003E63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB30_TLBSYNC	0x000003E7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB30_TLBSTATUS	0x000003E7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB30_PMEVCNTR0	0x000003EE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB30_PMEVCNTR1	0x000003EE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB30_PMEVCNTR2	0x000003EE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB30_PMEVCNTR3	0x000003EE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB30_PMEVTYPER0	0x000003EE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB30_PMEVTYPER1	0x000003EE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB30_PMEVTYPER2	0x000003EE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB30_PMEVTYPER3	0x000003EE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB30_PMCFGR	0x000003EF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB30_PMCR	0x000003EF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB30_PMCEID	0x000003EF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB30_PMCNTENSE	0x000003EF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB30_PMCNTENCLR	0x000003EF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB30_PMCNTENSET	0x000003EF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB30_PMINTENCLR	0x000003EF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB30_PMOVSCLR	0x000003EF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB30_PMOVSSET	0x000003EF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb30_pmauthstatus	0x000003EFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB31_SCTLR	0x000003F000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB31_ACTLR	0x000003F004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB31_RESUME	0x000003F008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB31_TCR2	0x000003F010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB31_TTBR0_low	0x000003F020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB31_TTBR0_high	0x000003F024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB31_TTBR1_low	0x000003F028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB31_TTBR1_high	0x000003F02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB31_TCR_lpae	0x000003F030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB31_CONTEXTIDR	0x000003F034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB31_PRRR_MAIR0	0x000003F038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB31_NMRR_MAIR1	0x000003F03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB31_FSR	0x000003F058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB31_FSRRESTORE	0x000003F05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB31_FAR_low	0x000003F060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB31_FAR_high	0x000003F064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB31_FSYNR0	0x000003F068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB31_IPAFAR_low	0x000003F070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB31_IPAFAR_high	0x000003F074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB31_TLBIVA_low	0x000003F600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB31_TLBIVA_high	0x000003F604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB31_TLBIVAA_low	0x000003F608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB31_TLBIVAA_high	0x000003F60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB31_TLBIASID	0x000003F610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB31_TLBIALL	0x000003F618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB31_TLBIVAL_low	0x000003F620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB31_TLBIVAL_high	0x000003F624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB31_TLBIVAAL_low	0x000003F628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB31_TLBIVAAL_high	0x000003F62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB31_TLBIIPAS2_low	0x000003F630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB31_TLBIIPAS2_high	0x000003F634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB31_TLBIIPAS2L_low	0x000003F638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB31_TLBIIPAS2L_high	0x000003F63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB31_TLBSYNC	0x000003F7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB31_TLBSTATUS	0x000003F7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB31_PMEVCNTR0	0x000003FE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB31_PMEVCNTR1	0x000003FE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB31_PMEVCNTR2	0x000003FE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB31_PMEVCNTR3	0x000003FE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB31_PMEVTYPER0	0x000003FE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB31_PMEVTYPER1	0x000003FE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB31_PMEVTYPER2	0x000003FE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB31_PMEVTYPER3	0x000003FE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB31_PMCFGR	0x000003FF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB31_PMCR	0x000003FF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB31_PMCEID	0x000003FF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB31_PMCNTENSE	0x000003FF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB31_PMCNTENCLR	0x000003FF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB31_PMCNTENSET	0x000003FF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB31_PMINTENCLR	0x000003FF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB31_PMOVSCLR	0x000003FF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB31_PMOVSSET	0x000003FF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb31_pmauthstatus	0x000003FFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions