SDSoC Platform Hardware Description

The hardware system is contained in the Vivado project <sdx_root>/samples/sdspfm/zc702_acp/src/vivado/zc702_acp.xpr.

The block diagram looks similar to the following figure.

Figure: ZC702_acp Block Diagram
As described in SDSoC Tcl Commands in Vivado, the hardware platform port interface is defined in the Vivado project, and is extracted by the SDSoC Platform Utility using Tcl commands which are contained in the script file src/vivado/zc702_acp_pfm.tcl. The following commands create a hardware platform object, give the platform a name and provide a brief description.
```
set pfm [sdsoc::create_pfm zc702_acp.hpfm]
sdsoc::pfm_name        $pfm "xilinx.com" "xd" "zc702_acp" "1.0"
sdsoc::pfm_description $pfm "Zynq XC702 platform with shared GP and ACP ports"
```
This command declares the default platform clock to have id 2. The 'true' argument indicates that this clock is the platform default.
```
sdsoc::pfm_clock       $pfm FCLK_CLK2 ps7 2 true  psr2
```
Tip: The command also specifies the associated proc_sys_reset IP instance (psr2) that is required of every platform clock as discussed in Declaring Clocks.
The following commands declare the platform AXI interfaces:
```
sdsoc::pfm_axi_port    $pfm M_AXI_GP0 ps7 M_AXI_GP
sdsoc::pfm_axi_port    $pfm S_AXI_HP0 ps7 S_AXI_HP
sdsoc::pfm_axi_port    $pfm S_AXI_HP1 ps7 S_AXI_HP
sdsoc::pfm_axi_port    $pfm S_AXI_HP2 ps7 S_AXI_HP
sdsoc::pfm_axi_port    $pfm S_AXI_HP3 ps7 S_AXI_HP
for {set i 1} {$i < 64} {incr i} {
  sdsoc::pfm_axi_port  $pfm M[format %02d $i]_AXI axi_ic_gp0 M_AXI_GP
}
for {set i 1} {$i < 8} {incr i} {
  sdsoc::pfm_axi_port  $pfm S[format %02d $i]_AXI axi_ic_acp S_AXI_ACP
}
```
Each AXI port requires a "memory type" declaration, which must be one of {M_AXI_GP, S_AXI_ACP, S_AXI_HP, MIG}, i.e., a general purpose AXI master, a cache coherent slave interface, a high-performance port or an interface to an external memory controller, respectively.

The for loop with API calls to the Mxy_AXI (y > 0) ports declares available master ports on the interconnect attached to the M_AXI_GP0 port of the processing system, and the loop with API calls to the Sxy_AXI (y > 0) ports declares available slave ports on the interconnect attached to the S_AXI_ACP port of the processing system.

Also observe in the Vivado block diagram shown above that the platform uses the least significant indexed ports on each of the interconnects within the platform as required.

The following commands declare the interrupt inputs:

for {set i 0} {$i < 16} {incr i} {
  sdsoc::pfm_irq       $pfm In$i irq_f2p
}

The following command creates the zc702_acp.hpfm hardware platform metadata file when the platform is generated by the SDSoC Platform Utility.
```
sdsoc::generate_hw_pfm $pfm
```
When this platform is used, the sdscc compiler will expand the platform interconnects attached to the M_AXI_GP0 and S_AXI_ACP ports as needed, which in effect share the CPU and DDR memory access between platform and SDSoC application logic.