Bitwise AND

The xFbitwise_and function performs the bitwise AND operation for each pixel between two input images, and returns an output image.
Where,
  • is the intensity of output image at (x, y) position
  • is the intensity of first input image at (x, y) position
  • is the intensity of second input image at (x, y) position

API Syntax

template<int SRC_T, int ROWS, int COLS, int NPC=1> 
void xFbitwise_and (
xF::Mat<int SRC_T, int ROWS, int COLS, int NPC> src1, 
xF::Mat<int SRC_T, int ROWS, int COLS, int NPC> src2, 
xF::Mat<int SRC_T, int ROWS, int COLS, int NPC> dst )

Parameter Descriptions

The following table describes the template and the function parameters.

Table 1. xFbitwise_and Function Parameter Descriptions
Parameter Description
SRC_T Input and output pixel type. Only 8-bit, unsigned, 1 channel is supported (XF_8UC1)
ROWS Maximum height of input and output image (must be a multiple of 8)
COLS Maximum width of input and output image (must be a multiple of 8)
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively.
src1 Input image
src2 Input image
dst Output image

Resource Utilization

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2017.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.

Table 2. xFbitwise_and Function Resource Utilization Summary
Operating Mode

Operating Frequency (MHz)

 Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 pixel 300 0 0 62 44 10
8 pixel 150 0 0 59 72 13

Performance Estimate

The following table summarizes the performance in different configurations, as generated using Vivado HLS 2017.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.

Table 3. xFbitwise_and Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7