Hardware Component Requirements

The hardware design in the Vitis unified software platform should adhere to the following rules:

• Every hardware platform design must contain a Processing System IP block from the IP catalog.

  Note:

  • Zynq® UltraScale+™ MPSoC and Zynq-7000 SoC devices are supported.
  • MicroBlaze processors are not supported for acceleration kernels, but can be part of the base hardware.
• Every IP used in the platform design that is not part of the standard Vivado® IP catalog must be local to the Vivado Design Suite project. References to IP repository paths external to the project are not supported by the write_hw_platform command.
• Any external hardware port interface to the Vitis platform must be an AXI4, AXI4-Lite, AXI4-Stream, clock, reset type interface.
  • Custom bus-type or hardware interfaces must remain internal to the platform design and cannot be declared for use by the v++ linker.

• Every platform must declare at least one general-purpose AXI master port from the Processing System IP, or have an interconnect IP connected to such an AXI master port. These are used for software control of accelerator IP.

  • sptags are supported for S_AXI interfaces that map memory. M_AXI_GP port sptags are not supported.
• Memory access through the MIG controller must use the PFM.AXI_PORT property and specify the memport, sptag, and a memory field containing the memory instance name and address range, as shown in the following example:

  set_property PFM.AXI_PORT {
  M_AXI_HPM1_FPD {memport "M_AXI_GP"} 
  S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "HPC0" memory "ps_e HPC0_DDR_LOW"}  
  S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "HPC1" memory "ps_e HPC1_DDR_LOW"}  
  S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "ps_e HP0_DDR_LOW"}  
  S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "ps_e HP1_DDR_LOW"}  
  S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP2" memory "ps_e HP2_DDR_LOW"}
  } [get_bd_cells /ps_e]

  • Kernel-to-Kernel, Host-to-Kernel, and multiple PL memory controllers are supported.

  • HLS kernels default to AXI4-MM interfaces which must use contiguous memory. The XRT memory allocator provides contiguous buffers.

  Note: Explicit connection points for XRT kernel attachment are specified with the PFM.AXI_PORT sptag interface property and a matching connectivity.sp command argument to the v++ linker.
• Streaming kernel interfaces are specified with the PFM.AXIS_PORT sptag interface property and a matching connectivity.sc command argument to the v++ linker.
• Sharing an AXI port, such as the S_AXI_HP0 port, between the Vitis compiler and other platform logic is accomplished by attaching an AXI interconnect IP or AXI SmartConnect IP block to the AXI port.
  • The internal platform logic must use the least significant indexes of the interconnect IP , leaving the remaining indexes enabled for use by the v++ linker in connecting the accelerator IP.
• Every platform must provide and declare one or more clock nets sourced within the platform. Multiple clocks are supported to enable additional internal clocks as needed to support the platform logic. These internal clocks can optionally be declared for use by the v++ linker for connecting accelerator IP.
  • Every declared platform clock must have an accompanying Processor System Reset IP block from the Vivado IP catalog.
  • The PFM.CLOCK property is used to set clocking and associated reset information.
  • Your design must identify one clock as the default clock, with id=0 and status=fixed.
  • If available, a clock with id=1 and status=fixed will be used by the v++ linker to connect to the ap_clk2 port of an acceleration kernel.
  • Frequencies of either clock are unspecified, but the designer should consider device and timing constraints.
• Platform interrupt inputs can use an AXI interrupt controller (axi_intc) IP block connected to the Processing System. IP blocks within an embedded processor platform can use up to 32 available fabric interrupts.
  Note: In the 2019.2 release, platform developers are responsible for wiring accelerator interrupts with the Processing subsystem IP for use by XRT using the dynamic_postlink.tcl script as described in Adding Kernel Interrupt Support. Do not declare any PFM.IRQ properties.