Creating the Hardware Component

1. Connect pl_clk0 to maxihpm0_fpd_aclk and maxihpm1_fpd_aclk.
2. Validate the design by clicking the box with a check mark icon on the IP integrator icon menu.

   

3. In the Sources view, right-click BD design (design_1.bd) and select Generate Output Products.
   1. Use default settings for Synthesis Options: Out-of-context per IP.
   2. Use default settings for Run Settings: On local host.
   3. Click Generate.
   4. On the Design Runs tab, expand the Out-of-Context Module Runs and observe a green check mark next to the design name when generation is complete.
4. In the Sources view, right-click BD design and select Create HDL Wrapper.
   1. Use default options settings: Let Vivado manage wrapper and auto-update.
   2. Click OK.
5. In the Flow Navigator, select Program and Debug > Generate Bitstream.
   1. Click Yes to launch synthesis and implementation.
   2. Use defaults on the Launch Runs dialog and click OK.
   3. Observe Bitstream Generation Completed message, click Cancel to continue.
6. Export the hardware design by selecting File > Export > Export Hardware.
   1. Click Include bitstream.
   2. Leave defaults for other settings.
   3. Click OK.
7. Observe that an XSA (design_1_wrapper.xsa) has been generated and placed in the Vivado project directory.

You have finished creating the XSA containing the hardware specification for use with the Vitis embedded software development flow. A Vitis software application can be created using this XSA.

If this XSA will be used for a Linux application, continue with Creating the Software Component, otherwise go to Creating the Platform.

1. Double-click the Zynq UltraScale+ MPSoC block in the IP integrator diagram.
2. Select Page Navigator > PS-PL Configuration.
3. Expand PS-PL Configuration > PS-PL Interfaces by clicking the > symbol.
4. Expand Master Interface.
5. Uncheck the AXI HPM0 FPD and AXI HPM1 FPD interfaces.
6. Click OK.
7. Confirm that the IP block interfaces were removed from the Zynq UltraScale+ MPSoC symbol in your block design.

   

1. Add Clocks to the block design:
   1. Click the Add IP command, or the '+' button, and search for and add a Clocking Wizard from the IP Search dialog.
   2. Double-click the clk_wiz_0 IP block to open the Re-Customize IP dialog box.
   3. Click the Output Clocks tab.
   4. Enable clk_out1 through clk_out5 in the Output Clock column, and set the Requested Output Freq as follows:
      • clk_out1 to 100 MHz.
      • clk_out2 to 200 MHz.
      • clk_out3 to 300 MHz.
      • clk_out4 to 400 MHz.
      • clk_out5 to 500 MHz.
   5. At the bottom of the dialog box set the Reset Type to Active Low.
   6. Click OK to close the dialog.
2. Add the Processor System Reset blocks:
   1. Click the Add IP command, or the '+' button, and search for and add a Processor System Reset from the IP Search dialog.
   2. Add four more Processor System Reset blocks, using the previous step; or select the proc_sys_reset_0 block and Copy (Ctrl-C) and Paste (Ctrl-V) it four times in the block diagram.
3. Connect Clocks and Resets:
   1. Click Run Connection Automation, which will open a dialog that will help connect the proc_sys_reset blocks to the clocking wizard clock outputs.
   2. Enable All Automation on the left side of the Run Connection Automation dialog box.
   3. Select clk_in1 on clk_wiz_0, and set the Clock Source to /zynq_ultra_ps_e_0/pl_clk0
   4. For each proc_sys_reset instance, select the slowest_sync_clk, and set the Clock Source as follows:
      • proc_sys_reset_0 with /clk_wiz_0/clk_out1
      • proc_sys_reset_1 with /clk_wiz_0/clk_out2
      • proc_sys_reset_2 with /clk_wiz_0/clk_out3
      • proc_sys_reset_3 with /clk_wiz_0/clk_out4
      • proc_sys_reset_4 with /clk_wiz_0/clk_out5
   5. On each proc_sys_reset instance, select the ext_reset_in, and set the Select Manual Source to /zynq_ultra_ps_e_0/pl_resetn0.
   6. Make sure all checkboxes are enabled, and click OK to close the dialog and create the connections.
4. Connect all the dcm_locked signals on each proc_sys_reset instance to the locked signal on clk_wiz_0.

After completing the steps above, your block design should look like the following figure.

Next you will add the target platform properties and declare the interfaces available to the v++ linker for integrating application acceleration kernels with the base hardware platform.

1. Expand the zynq_ultra_ps_e_0 block in the Platform interfaces view, and enable all interfaces by right-clicking an interface and selecting Enable, except the following interfaces, which should remain disabled:
   • S_AXI_ACP_FPD.
   • S_AXI_LPD.
   • pl_clk0.
2. Expand the clk_wiz_0 block and enable all clocks, clk_out1 through clk_out5.
3. Select clk_out3 and define it as the default clock for the platform by editing its properties in the Platform Interface Properties view.
   1. Select the Options tab.
   2. Set id = 0.
      IMPORTANT: You must click Enter to finalize changes after edits.
   3. Select is_default by clicking the box.
   4. Ensure status = fixed.

After specifying the various platform interfaces, you must set project properties, optionally enable emulation, validate the block design, generate output files, and generate the required XSA.

1. You must also set project properties to inform downstream tools of the intended use of the target platform's hardware design using the Tcl console to enter the following commands:

   set_property platform.design_intent.embedded true [current_project]
   set_property platform.design_intent.server_managed false [current_project]
   set_property platform.design_intent.external_host false [current_project]
   set_property platform.design_intent.datacenter false [current_project]
   set_property platform.default_output_type "sd_card" [current_project]
   

2. This is an optional step to add hardware emulation support to your platform. Select the zynq_ultra_ps_e_0 block and in the Block Properties view change the SELECTED_SIM_MODEL property from rtl to tlm.
   TIP: You can also do this using the following Tcl command:

   set_property SELECTED_SIM_MODEL tlm [get_bd_cells /zynq_ultra_ps_e_0]

3. Validate the block design by right-clicking the IP integrator canvas and selecting Validate Design.
4. In the Sources view, right-click BD design (design_1.bd) and select Generate Output Products.
   1. Use default settings for Synthesis Options: Out-of-context per IP.
   2. Use default settings for Run Settings: On local host.
   3. Click Generate.
   4. On the Design Runs tab, expand the Out-of-Context Module Runs and observe a green check mark next to the design name when generation is complete.
5. In the Sources view, right-click BD design and select Create HDL Wrapper.
   1. Use default options settings: Let Vivado manage wrapper and auto-update.
   2. Click OK.
6. In the Flow Navigator, select Program and Debug > Generate Bitstream.
   1. Click Yes to launch synthesis and implementation.
   2. Use defaults on the Launch Runs dialog and click OK.
   3. Observe Bitstream Generation Completed message, click Cancel to continue.
7. Create the XSA with the following Tcl command:

   write_hw_platform -include_bit zcu102_min.xsa

8. Validate the XSA:

   validate_hw_platform ./zcu102_min.xsa

9. Observe that an XSA (zcu102_min.xsa) has been generated and placed at the same level as the Vivado project directory.

An XSA with kernel support has now been created and can be used as the hardware component in a Vitis target platform project to provide kernel-based application acceleration. The target platform also requires a software component. The PetaLinux tools are used to generate the Linux software components and include the XRT library support with the additions shown in Creating the Software Component.