Configuring Platform Interface Properties

You can export any clock source with the platform, but for each clock you must also export synchronized reset signals using a Processor System Reset IP block in the platform. The PFM.CLOCK property can be set on a BD cell, external port, or external interface.

The Tcl command for setting the PFM.CLOCK property is:

set_property PFM.CLOCK { <port_name> {parameters} \
<port2> {parameters} ...} [get_bd_cells <cell_name>]

Argument Description

Port_name

Clock port name

Parameters

• id <value>: Clock ID is a user-defined value that must be a unique non-negative integer.

• is_default <value>: Specify true if this is the default clock, false otherwise. The default is false.

• proc_sys_reset <value>: This name/value pair specifies the corresponding proc_sys_reset block instance for synchronized reset signals connected to the clock port.

• status <value>: Value can be fixed or scalable. A fixed clock can serve as a reference clock for generated clocks. Embedded platforms must use fixed.

Examples:

set_property PFM.CLOCK {
PL_CLK0 {id "0" is_default "true" proc_sys_reset \
"proc_sys_reset_0" status "fixed"} 
PL_CLK1 {id "1" is_default "false" proc_sys_reset \
"proc_sys_reset_1" status "fixed"} 
PL_CLK2 {id "2" is_default "false" proc_sys_reset \
"proc_sys_reset_2" status "fixed"} 
PL_CLK3 {id "3" is_default "false" proc_sys_reset \
"proc_sys_reset_3" status "fixed"} 
} [get_bd_cells /zynq_ultra_ps_e_0]

To set a CLOCK on an external PORT:

set_property PFM.CLOCK
{ACLK_0 {id "4" is_default "false" proc_sys_reset \
"proc_sys_reset_4"}} [get_bd_ports /ACLK_0]

The Tcl command for setting the PFM.AXI_PORT property is:

set_property PFM.AXI_PORT { <port_name> {parameters} \
<port2> {parameters} ...} [get_bd_cells <cell_name>]

Argument Description

Port_name

AXI port name

Parameters

• memport type: Corresponding memory interface port type. Valid type values include:
  • M_AXI_GP: A general-purpose AXI master port
  • S_AXI_HP: A high-performance AXI slave port
  • S_AXI_ACP: An accelerator coherent slave port
  • S_AXI_HPC: A high-performance accelerator coherent slave port
  • MIG: An AXI slave connected to a MIG memory controller. The default is MIG.
• sptag ID: (Optional) A user-defined ID that should start with an alphabetic character. The ID is case-sensitive. The system port tag (sptag) is a symbolic identifier that represents a class of platform port connections, such as S_AXI_HP, S_AXI_ACP, M_AXI_GP. Multiple block design platform ports can share the same sptag.
• memory: (Optional) Specify the associated MIG IP instance and address_segment. The memory tag is a unique identifier that combines the Cell name and Base Name columns in the IP integrator Address Editor. This tag will be associated with connections to the Memory Subsystem HIP, where multiple block design platform ports can share the same memory tag.

Example for an AXI Interconnect

set_property PFM.AXI_PORT { \
	M_AXI_GP0 {memport "M_AXI_GP"} \
	M_AXI_GP1 {memport "M_AXI_GP"} \
	S_AXI_ACP {memport "S_AXI_ACP" sptag "ACP" memory \
"processing_system7_0 ACP_DDR_LOWOCM"} \
	S_AXI_HP0 {memport "S_AXI_HP" sptag "HP0" memory \
"processing_system7_0 HP0_DDR_LOWOCM"} \
	S_AXI_HP1 {memport "S_AXI_HP" sptag "HP1" memory \
"processing_system7_0 HP1_DDR_LOWOCM"} \
	S_AXI_HP2 {memport "S_AXI_HP" sptag "HP2" memory \
"processing_system7_0 HP2_DDR_LOWOCM"} \
	S_AXI_HP3 {memport "S_AXI_HP" sptag "HP3" memory \
"processing_system7_0 HP3_DDR_LOWOCM"} \
	} [get_bd_cells /processing_system7_0]

Exporting AXI interconnect master and slave ports involves the following requirements:

• All ports on the interconnect used within the platform must precede in index order any declared platform interfaces.
• There can be no gaps in the port indexing.
• The maximum number of master IDs for the S_AXI_ACP port is 8, so on a connected AXI interconnect, available ports to declare must be one of {S00_AXI, S01_AXI, ..., S07_AXI}. Do not declare any ports that are used within the platform itself. Declaring as many as possible will allow sds++ to avoid cascaded axi_interconnects.
• The maximum number of master IDs for an S_AXI_HP or MIG port is 16, so on an connected AXI interconnect, available ports to declare must be one of {S00_AXI, S01_AXI, ..., S15_AXI}. Do not declare any ports that are used within the platform itself. Declaring as many as possible will allow sds++ to avoid cascaded axi_interconnects in generated user systems.
• The maximum number of master ports declared on an interconnect connected to an M_AXI_GP port is 64, so on an connected AXI interconnect, available ports to declare must be one of {M00_AXI, M01_AXI, ..., M63_AXI}. Do not declare any ports that are use within the platform itself. Declaring as many as possible will allow sds++ to avoid cascaded axi_interconnects in generated user systems.

Additional Examples

To define an AXI_port on interconnect:

set parVal []
for {set i 2} {$i < 64} {incr i} {
	lappend parVal M[format %02d $i]_AXI \
{memport "M_AXI_GP"}
}
set_property PFM.AXI_PORT $parVal [get_bd_cells /axi_interconnect_0]

To define an AXI_port on SmartConnect IP:

set parVal []
for {set i 1} {$i < 16} {incr i} {
	lappend parVal S[format %02d $i]_AXI \
{memport "MIG" sptag "Bank0"}
}
set_property PFM.AXI_PORT $parVal [get_bd_cells /smartconnect_0]

To define an AXI_PORT that connects with MIG IP:

set parVal []
for {set i 1} {$i < 16} {incr i} {
	lappend parVal S[format %02d $i]_AXI \
{memport "MIG" sptag "bank0" memory "ddrmem_0 C0_DDR4_ADDRESS_BLOCK"}
}
set_property PFM.AXI_PORT $parVal [get_bd_cells \
/memory_subsystem/interconnect_data/interconnect_aximm_ddrmem0]

Argument Description

Port_name

AXI4-Stream port name.

Parameters

• type value: Streaming interface port type. Valid values for type include:
  • M_AXIS: A general-purpose AXI master port
  • S_AXIS: A high-performance AXI slave port

Examples

set_property PFM.AXIS_PORT {AXIS_P0 {type "S_AXIS"}} \
[get_bd_cells /zynq_ultra_ps_e_0]