Platform Add-Ons

Adding Kernel Interrupt Support

You can provide kernel interrupt support by adding an AXI interrupt controller to the base hardware design and connecting the output of the interrupt controller to the input of the processor block interrupt. The interrupt inputs of the AXI interrupt controller are initialized to a de-asserted state by wiring them to ground. When the v++ linker adds acceleration kernels to the base hardware design, the dynamic_postlink.tcl script is used to wire the interrupt output of the kernel to the AXI interrupt controller.

The following steps include obtaining and using the dynamic_postlink.tcl. If you want to add kernel interrupts, add the following IP to the IP integrator block diagram prior to writing the XSA. To use the dynamic_postlink.tcl script, the hierarchy, IP names, and net names within the block diagram must match the script.

  1. Re-customize the Zynq UltraScale+ MPSoC IP block and enable the M_AXI_HPM0_LPD interface for use by the base hardware design.
    1. In the block diagram, double-click the Zynq UltraScale+ MPSoC block.
    2. Select PS-PL Configuration > PS-PL interfaces > Master interface.
    3. Select the AXI HPM0 LPD check box.

    Observe that M_AXI_HPM0_LPD and maxihpm0_lpd_aclk ports were added.

  2. Connect maxihpm0_lpd_aclk to /clk_wiz_0/clk_out3.
  3. Delete any existing xlconcat blocks connected to the processor so that your IP instances names correspond with the dynamic_postlink.tcl script.
  4. Add Concat IP:
    1. Right-click the IP block diagram and select Add IP.
    2. Search for concat.
    3. With Concat selected, press the Enter key.
  5. Re-customize Concat IP:
    1. Double-click the Concat block to open the Re-Customize IP dialog box.
    2. Set the number of ports to 32.
    3. Click OK.
  6. Add the Constant IP block:
    1. Right-click the IP block diagram and select Add IP.
    2. Search for constant.
    3. With Constant selected, press the Enter key.
  7. Re-customize Constant IP:
    1. Double-click the Constant block to open the Re-Customize IP dialog box.
    2. Set Const Width =1.
    3. Set Const Val = 0.
    4. Click OK.
  8. Connect the xlconstant_0 dout[0:0] output to all 32 inputs of xlconcat_0:
    1. Ctrl-click on each xlconcat_0 input pin to select them.
    2. Right-click one of the selected xlconcat_0 input pins and select Make Connection.
    3. In the Make Connection dialog box, scroll to and select the xlconstant_0 dout pin.
    4. Click OK.
  9. Rename the xlconstant_0 and xlconcat_0 IP instance names to match the dynamic_postlink.tcl script.
    1. Select the xconstant_0 IP block.
    2. In the Block Properties, General dialog box, change the name to xlconstant_gnd.
    3. Select the xlconcat_0 IP block.
    4. In the Block Properties, General dialog box, change the name to xlconcat_interrupt_0.
  10. Make a hierarchical sub-block from the xlconstant_gnd and xlconcat_interrupt_0 blocks. Ensure that the net connecting the xlconstant_gnd and the xlconcat_interrupt_0 blocks is named xlconstant_gnd_dout in order to match the dynamic_postlink.tcl script.
    1. Select the xlconstant_gnd and xcloncat_interrupt_0 blocks.
    2. Right-click your selection and select Create Hierarchy.
    3. In the Create Hierarchy dialog box, set the Cell name to interrupt_concat.
    4. Click OK.
  11. Click (+) to expand the interrupt_concat block and create a port from the dout signal bus.
    1. Select the dout[31:0] pin on the xlconcat_interrupt_0 block.
    2. Right-click your selection and select Create Port.
    3. Leave the default settings and click OK.
    4. Remove the external port connection wire and port name from the top-level IP diagram.
  12. Add the AXI Interrupt Controller IP block:
    1. Right-click IP block diagram and select Add IP.
    2. Search for intc, and with the AXI Interrupt Controller selected, press the Enter key.
  13. Re-customize the AXI Interrupt Controller IP block:
    1. Double-click the AXI Interrupt Controller block to open the Re-Customize IP dialog box.
    2. Set the Interrupts type to Level by changing the button to Manual and entering 0x0 text field.
    3. Set the Level type to High by changing the button to Manual and entering 0xFFFFFFFF.
    4. Set the Interrupt Output Connection to Single.
    5. Click OK.
  14. Use Run Connection Automation to connect the AXI Interrupt Controller s_axi bus to the Zynq UltraScale+ MPSoC M_AXI_HPM0_LPD port.
    1. Leave the default values for Master interface and Bridge IP.
      • Master interface default is /zynq_ultra_ps_e_0/M_AXI_HPM0_LPD.
      • Bridge IP default is New AXI interconnect.
    2. For the clock source for driving Bridge IP, select /clk_wiz_0/clk_out3. This is the default acceleration kernel clock.
    3. For the clock source for Slave interface, select /clk_wiz_0/clk_out3.
    4. Notice that the clock source for Master interface default is /clk_wiz_0/clk_out3 because we wired it to the PS block earlier.
    5. Click OK.
  15. Connect the AXI Interrupt Controller interrupt input by wiring the interrupt_concat/dout[31:0] to the axi_intc_0/intr[0:0] input.
  16. Connect the AXI Interrupt Controller interrupt output by wiring the axi_intc_0/irq output to the Zynq UltraScale+ MPSoC pl_ps_irq0[0:0] input.

    The following block diagram shows the completed system wired with the interrupt controller.

  17. Set the platform design intent properties. These properties can also be queried.
    set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]

get_property platform.design_intent.embedded [current_project]
get_property platform.design_intent.server_managed [current_project]
get_property platform.design_intent.external_host [current_project]
get_property platform.design_intent.datacenter [current_project]
  18. Set the platform default output type property.
    
set_property platform.default_output_type "sd_card" [current_project]

get_property platform.default_output_type [current_project]
  19. Get dynamic_postlink.tcl script from the Xilinx Run Time (XRT) repository:
    1. In a Web browser, navigate to https://github.com/Xilinx/XRT/tree/master/src/platform/zcu102_base.
    2. Save the dynamic_postlink.tcl file in the directory containing your Vivado project.
  20. Edit the dynamic_postlink.tcl script you just saved in the Vivado project to ensure that the script and IP diagram processor names match. To do this, change the two instances of ps_* to zynq_ultra_ps_*.
  21. Add the platform property to use dynamic_postlink.tcl during the v++ link:
    set_property platform.post_sys_link_tcl_hook ./dynamic_postlink.tcl [current_project]
  22. Ensure that M_AXI_HPM0_LPD is disabled for use by the v++ linker because it is being used in the base hardware design:
    1. Select M_AXI_HPM0_LPD in the Window > Platform Interfaces view.
    2. Right-click your selection and select Disable.
  23. Right-click and select Validate Design on IP integrator diagram.
  24. Select the Zynq UltraScale+ MPSoC IP block and set SELECTED_SIM_MODEL to tlm in the Block Properties view.
  25. Save the block design.
  26. Right-click design_1.bd in the Block Design, Sources view and select Generate Output Products.
  27. Create the HDL wrapper:
    1. Right-click design_1.bd in the Block Design, Sources view and select Create HDL Wrapper.
    2. Select Let Vivado manage wrapper and auto-update.
    3. Click OK.
  28. In the Flow Navigator view, generate the bitstream:
    1. Click Program and Debug > Generate Bitstream.
    2. Click Yes to launch synthesis and implementation.
    3. In the Launch Runs dialog box, leave the defaults and click OK.
  29. Create the XSA:
    write_hw_platform -include_bit -force zcu102_min.xsa
  30. Validate the XSA: 
    validate_hw_platform ./zcu102_min.xsa