cosim_design

Description

Executes post-synthesis co-simulation of the synthesized RTL with the original C-based test bench.

To specify the files for the test bench run the following command:

add_files -tb

The simulation results are written to the sim/Verilog or sim/VHDL folder of the active solution, depending on the setting of the -rtl option.

Syntax

cosim_design [OPTIONS]

Options

-O
Enables optimize compilation of the C test bench and RTL wrapper. This increases compilation time, but results in better runtime performance.
-argv <string>
The <string> is passed onto the main C function.

Specifies the argument list for the behavioral test bench.

-compiled_library_dir <string>
Specifies the compiled library directory during simulation with third-party simulators. The <string> is the path name to the compiled library directory.
-coverage

Enables the coverage feature during simulation with the VCS simulator.

-disable_deadlock_detection
Disables the deadlock detection feature in co-simulation.
-enable_dataflow_profiling
This option turns on the dataflow channel profiling to track channel sizes during co-simulation.
-ldflags <string>

Specifies the options passed to the linker for co-simulation.

This option is typically used to pass include path information or library information for the C test bench.

-mflags <string>

Specifies options required for simulation.

-random_stall
Enable random stalling of top-level interfaces during co-simulation.
-rtl [verilog | vhdl]
Specifies which RTL language to use for C/RTL co-simulation. The default is Verilog.
-setup
Creates all simulation files created in the sim/<HDL> directory of the active solution. The simulation is not executed, but can be run later from a command shell.
-tool [*auto* | vcs | modelsim | riviera | isim | xsim | ncsim | xceilum]

Specifies the simulator to use to co-simulate the RTL with the C test bench.

-trace_level [*none* | all | port | port_hier]

Determines the level of waveform trace data to save during C/RTL co-simulation.

  • none does not save trace data. This is the default.
  • all results in all port and signal waveforms being saved to the trace file.
  • port only saves waveform traces for the top-level ports.
  • port_hier save the trace information for all ports in the design hierarchy.

The trace file is saved in the sim/Verilog or sim/VHDL folder of the current solution when the simulation executes, depending on the selection used with the -rtl option.

-wave_debug
Enables the waveform visualization of all processes in the generated RTL, as in the dataflow and sequential processes. This is only supported when using Vitis Simulator for co-simulation. See Viewing Simulation Waveforms for more information.

Examples

Performs verification using the Vivado Simulator:
cosim_design
Uses the VCS simulator to verify the Verilog RTL and enable saving of the waveform trace file:
cosim_design -tool VCS -rtl verilog -coverage -trace_level all
Verifies the VHDL RTL using ModelSim. Values 5 and 1 are passed to the test bench function and used in the RTL verification:
cosim_design -tool modelsim -rtl vhdl -argv "5 1"