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Vitis Unified Software Development Platform 2020.1 Documentation
  • Vitis Application Acceleration Development Flow Documentation
  • Vitis Embedded Software Development Flow Documentation
  • Vitis HLS
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  1. Home
  2. Vitis Embedded Software Development Flow Documentation
  3. Xilinx Software Command-Line Tool
  4. XSCT Commands
  5. JTAG UART
  • Vitis Embedded Software Development Flow Documentation
    • Getting Started
    • Develop
    • Run, Debug, and Optimize
    • Vitis Utilities
    • Embedded Software Development Use Cases in the Vitis Software Platform
    • Bootgen Tool
    • Xilinx Software Command-Line Tool
      • Xilinx Software Command-Line Tool
      • XSCT Commands
        • Target Connection Management
        • Target Registers
        • Program Execution
        • Target Memory
        • Target Download FPGA/BINARY
        • Target Reset
        • Target Breakpoints/Watchpoints
        • JTAG UART
          • jtagterminal
          • readjtaguart
        • Miscellaneous
        • JTAG Access
        • Target File System
        • SVF Operations
        • Vitis Projects
      • XSCT Use Cases
      • Hardware Software Interface (HSI) Commands
    • Embedded Drivers and Libraries
    • Embedded Design Tutorials
    • PDF Version of Documentation

JTAG UART

The following is a list of streams commands:

  • jtagterminal
  • readjtaguart
  • jtagterminal
  • readjtaguart
Copyright 2019-2020 Xilinx Inc. UG1416 (v2020.1) 20 August 2020
PDFs: Accelerated application development | Embedded software development | Vitis HLS