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Vitis Unified Software Development Platform 2020.1 Documentation
Vitis Application Acceleration Development Flow Documentation
Vitis Embedded Software Development Flow Documentation
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Vitis Embedded Software Development Flow Documentation
Xilinx Software Command-Line Tool
XSCT Commands
Target Registers
Vitis Embedded Software Development Flow Documentation
Getting Started
Develop
Run, Debug, and Optimize
Vitis Utilities
Embedded Software Development Use Cases in the Vitis Software Platform
Bootgen Tool
Xilinx Software Command-Line Tool
Xilinx Software Command-Line Tool
XSCT Commands
Target Connection Management
Target Registers
rrd
rwr
Program Execution
Target Memory
Target Download FPGA/BINARY
Target Reset
Target Breakpoints/Watchpoints
JTAG UART
Miscellaneous
JTAG Access
Target File System
SVF Operations
Vitis Projects
XSCT Use Cases
Hardware Software Interface (HSI) Commands
Embedded Drivers and Libraries
Embedded Design Tutorials
PDF Version of Documentation
Target Registers
The following is a list of registers commands:
rrd
rwr
rrd
rwr