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Vitis Embedded Software Development Flow Documentation
Xilinx Software Command-Line Tool
XSCT Commands
Target File System
Vitis Embedded Software Development Flow Documentation
Getting Started with Vitis
Using the Vitis IDE
Bootgen Tool
Xilinx Software Command-Line Tool
Xilinx Software Command-Line Tool
XSCT Commands
Target Connection Management
Target Registers
Program Execution
Target Memory
Target Download FPGA/BINARY
Target Reset
IPI commands to Versal PMC
Target Breakpoints/Watchpoints
Jtag UART
Miscellaneous
JTAG Access
Target File System
tfile open
tfile close
tfile read
tfile write
tfile stat
tfile lstat
tfile fstat
tfile setstat
tfile fsetstat
tfile remove
tfile rmdir
tfile mkdir
tfile realpath
tfile rename
tfile readlink
tfile symlink
tfile opendir
tfile readdir
tfile copy
tfile user
tfile roots
tfile ls
SVF Operations
Device Configuration System
Vitis Projects
XSCT Use Cases
Hardware Software Interface (HSI) Commands
Drivers and Libraries
Embedded Design Tutorials
Additional Resources and Legal Notices
Target File System
tfile open
tfile close
tfile read
tfile write
tfile stat
tfile lstat
tfile fstat
tfile setstat
tfile fsetstat
tfile remove
tfile rmdir
tfile mkdir
tfile realpath
tfile rename
tfile readlink
tfile symlink
tfile opendir
tfile readdir
tfile copy
tfile user
tfile roots
tfile ls