JESD204C IP Core

  • 产品编号: JESD204C
  • 供应商: Comcores ApS
  • Partner Tier: Select


The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.


  • Full JESD204C feature set available
  • Link and transport layer available
  • 8B/10B, 64B/66B, 64B/80B encoding/decoding supported
  • Scrambling and de-scrambling included
  • Support for all subclasses (0, 1, 2)
  • Silicon proven
  • Lint/CDC optimized
  • UVM regression tested
  • Interoperability tested with leading PHY/Serdes vendors
  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • Strong engineering support for bring-up
  • Targeting any RTL implementation like ASICs, ASSPs and FPGAs



系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2018.1 Y 0 80455 4 2 0 0 490

IP 质量指标


数据创建日期 May 26, 2022
当前 IP 修订号 2.1.4
当前修订日期已发布 Apr 08, 2019
第一版发布日期 Dec 18, 2018

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 15
可否提供参考? N


可供购买的 IP 格式 Source Code, Netlist
源代码格式 Verilog
是否包含高级模型? N
模型格式 ,
提供集成测试台 Y
集成测试台格式 Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? XDC
商业评估板是否可用? Y
评估板所用的 FPGA Virtex UltraScale+
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 UltraFast Design Methodology
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Vivado Synthesis
是否执行静态时序分析? Y
AXI 接口 AXI4-Lite
是否包含 IP-XACT 元数据? Y


是否有可用的文档验证计划? Executable and documented plan
测试方法 Constrained random testing
断言 N
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Synopsys VCS; Mentor ModelSIM


在 FPGA 上进行验证 Y
所使用的硬件验证平台 VCU118
已通过的行业标准合规测试 N
是否提供测试结果? N