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DYPLO Dynamic Process Loader Core


Dyplo is a middleware solution to enable seamless integration of FPGA and software processes in applications. Dyplo links processes, executed on processor(s) and FPGA(s), with scalable software and hardware data streams embedded in the applied operating system. Dyplo managed processes, executed on FPGA fabric, share the same characteristics as software executed processes due to the extensive usage and support for partial reconfiguration, an advanced technology available in FPGAs. Using these properties, a full software-driven hardware development approach is made possible. This implies that the implementation of an application can be developed entirely in software while maintaining the software architecture, functions to be executed on FPGA fabric can be identified, isolated and replaced by FPGA functionality without compromising the program structure. This reduces to a high extend the low-level integration effort between FPGA and processor, which require development of bus interfaces, low level drivers and OS integration. With the partial reconfiguration FPGA fabric is reused in time, reducing the required FPGA size and as such reducing power requirements and FPGA cost.


  • Design abstraction to system level.
  • Dyplo Wizard confi guration tool to guarantee ease of use.
  • High level of reuse capabilities over designs.
  • Integrated support for high-level synthesis.
  • Simple use of partial reconfi guration blocks in hardware.
  • Software driven hardware development approach.
  • Utilization of SOC devices to their maximum.



系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z020 -1 Vivado 2015.4 Y 1503 3611 18 0 0 0 100

IP 质量指标


数据创建日期 Sep 25, 2017
当前 IP 修订号 2015.4
当前修订日期已发布 Feb 24, 2014
第一版发布日期 Apr 18, 2014

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 1
可否提供参考? Y


可供购买的 IP 格式 Source Code
源代码格式 VHDL
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL, C/C++
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? N
商业评估板是否可用? Y
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux


代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Xilinx XST / 2013.4
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream, AXI4
是否包含 IP-XACT 元数据? N


是否有可用的文档验证计划? Executable and documented plan
测试方法 Directed Testing
断言 N
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Xilinx lSim / 2013.4; Mentor Questa / Latest; Mentor ModelSIM / Latest


在 FPGA 上进行验证 Y
所使用的硬件验证平台 ZedBoard ZC702 ZC706
已通过的行业标准合规测试 N
是否提供测试结果? N