DYPLO Dynamic Process Loader Core


Applications can benefit from Dyplo® when FPGA based algorithmic acceleration is required to achieve software performance goals or manage FPGA implemented dynamic processing pipelines. Using Dyplo®, you reduce the complexity of programming FPGA fabric to the level of programming GPU devices using OpenCL coding style. The usage of FPGA fabric for software programmers feels like working with software threads When integrating functionality of applications running both on the processors as well as the FPGA fabric, require data to be exchanged/shared between the two entities. This is typically where expertise from different disciplines is needed: writing Linux kernel drivers, construction of proper DMA based data exchange mechanisms, high-performance FPGA interfaces according to strict bus protocols and software programming skills. Here multiple programming disciplines meet. To address this, TOPIC developed Dyplo®, a Dynamic Process Loader. On the FPGA side, Dyplo®forms a Network-on-Chip (NOC), wrapping fixed and dynamically exchangeable FPGA function blocks. On the processor side, Dyplo®is a Linux kernel driver/API that interfaces with the Dyplo®NOC using file baseddata streams. The third aspect of Dyplo®is the implementation flow to transform a software defined function block into a Dyplo®wrapped FPGA function block.


  • Intensive use of FPGA partial reconfiguration technology
  • Running software functions on FPGAs, programmed in an OpenCL style
  • Ideal for data-centric applications: database searches, algorithmic processing pipes
  • Accelerator deployment on FPGA with on-demand reconfiguration/reuse of logic
  • High-performance DMA interfaces for background memory and PCIe communication
  • FPGA programming using a simplified software development flow
  • Smaller FPGAs and less power usage by resource sharing
  • Self-repairing capabilities for automatic recovery from e.g. SEU failures
  • Special Dyplo variances for Aerospace and Fail-Safe applications