The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD, including 4K2K) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in embedded designs based on AMD MPSoC, SoC and FPGA devices. The logiISP-UHD IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. In addition to the standard IP core deliverables, Xylon offers licensable Auto White Balancing (AWB) and Auto Exposure (AE) processor-based control algorithms that work with the video analytics data collected by the ISP pipeline.
The logiISP IP core can be easily combined with the logiHDR High Dynamic Range (HDR) Pipeline IP core into advanced video processing pipeline capable to extract the maximum detail from high contrast scenes, i.e. scenes with objects highlighted by a direct sunlight and objects placed in extreme shades.
- Complete and configurable Ultra High Definition ISP pipeline
- Digitally processes and enhances the quality of an input video stream and collects video statistics data
- Evaluation IP core and the bit-accurate C model available on request
- IP deliverables include the software driver, documentation and technical support
- Configurable ISP blocks: Defective Pixel Correction, Color Filter Array Interpolation, Image Statistics, Image Enhancement, Color-Space Converters and others
- Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
- Input video formats: Raw Bayer, RGB and YCrCb; 8/10/12-bit per pixel
- Parallel pixel processing of 1, 2 or 4 pixels per clock
- Video input and output are ARM AMBA AXI4-Stream protocol compliant
- Fee-based license extension for the AWB&AE