PCI Express DMA Back-End Core (NWL)

  • 产品编号: DMA Back-End Core
  • 供应商: Rambus, Inc.
  • Member Partner


The Rambus DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. The core works with the Xilinx FPGA hard cores. It can be configured with multiple DMA Engines which each have their own interface. It supports Packet/Block and Addressed/Non-addressed transfers. Host-based and local descriptors are supported. The core supports legacy, MSI and MSI-X interrupts. Using the core eliminates the need for the user to implement their own DMA design, significantly reducing development time and risk. Companion Windows and Linux DMA drivers are available. The DMA Back-End Driver works hand-in-hand with the DMA Back-End core to implement host-based, scatter-gather DMA operation. Note: Utilization numbers provided in the 'IP Implementation and Quality Metrics' tab is for a x1 lane DMA Back-End Core implementation


  • Utilization numbers provided in the IP Implementation and Quality Metrics are for a x1 lane PCIe implementation
  • Provided with a PCI Express Testbench
  • Works with Xilinx PCI Express hard cores and Northwest Logic soft PCI Express cores
  • Fully hardware validated
  • Supports host-based and local descriptors
  • Supports Packet/Block and Addressed/Non-addressed transfers
  • Provides maximum DMA throughput in both System->Card and Card->System directions
  • Also available with AXI user interface
  • Companion Windows and Linux DMA Drivers available
  • Can be configured with multiple independent DMA Engines
  • Provides high performance, scatter-gather DMA operation



系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -1 Vivado 2018.3 Y 2794 7412 3 0 0 0 250

IP 质量指标


数据创建日期 Oct 05, 2022
当前 IP 修订号 4.24
当前修订日期已发布 Jun 07, 2016
第一版发布日期 Jul 07, 2007

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 283
可否提供参考? Y


可供购买的 IP 格式 Netlist, Source Code
源代码格式 Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? UCF
商业评估板是否可用? Y
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Windows, Linux


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference
定制 FPGA 优化技术 Optimized levels of logic for FPGA operation
所支持的综合软件工具及版本 Xilinx XST / All; Synplicity Synplify / All; Mentor Precision / All
是否执行静态时序分析? Y
是否包含 IP-XACT 元数据? N


是否有可用的文档验证计划? Yes, document only plan
测试方法 Both
断言 N
收集的覆盖指标 Code, Functional
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Mentor ModelSIM / All; Xilinx lSim / All; Cadence NC-Sim / All; Cadence IUS / All; Mentor Questa / All; Synopsys VCS / All; Other / ALdec RiveraPro/Active-HDL; Other / Synapticad Verilogger


在 FPGA 上进行验证 Y
所使用的硬件验证平台 multiple platforms
已通过的行业标准合规测试 Y
特定的合规测试 PCI-SIG Compliance Workshop
测试日期 Nov 19, 2008
是否提供测试结果? Y