DI2CM - I2C Bus Controller Master

产品描述

The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master transmitter or a master receiver, depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. A built-in timer allows operation from a wide range of the clk frequencies. The DI2CM is a technology independent design and can be implemented in various process technologies.


主要特性与优势

  • Scan test ready
  • No internal tri-states
  • Static synchronous design with positive edge clocking and synchronous reset
  • Fully synthesizable
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Host side interface dedicated for microproces-sors / microcontrollers
  • Built-in 8-bit timer for data transfers speed adjusting
  • Interrupt generation
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Support for multi-master systems
  • Arbitration and clock synchronization
  • Support for all transmission speeds - Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s) and High Speed (up to 3,4 Mb/s)
  • Master operation (Master transmitter, Master receiver)
  • Conforms to v.3.0 of the I2C specification

包裝內容物含配件

  • 3 months maintenance
  • Active-HDL automatic simulation macros
  • Datasheet
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Example application
  • HDL core specification
  • IP Core implementation support
  • Installation notes
  • ModelSim automatic simulation macros
  • Phone & email support
  • Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist
  • Synthesis scripts
  • Technical documentation
  • Technical support
  • Tests with reference responses
  • VHDL & VERILOG test bench environment

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU19EG -3 Vivado 2019.1 Y 40 223 0 0 0 0 550
KINTEX-U Family XCKU025 -3 Vivado 2019.1 Y 43 223 0 0 0 0 530
Spartan-7 Family XC7S75 -3 Vivado 2019.1 Y 69 224 0 0 0 0 520
KINTEX-7 Family XC7K70T -3 ISE 14.4 Y 67 207 0 0 0 0 511
ARTIX-7 Family XC7A100T -3 ISE 14.4 Y 79 174 0 0 0 0 327
Zynq-7000 Family XC7Z010 -3 Vivado 2019.1 Y 79 249 0 0 0 0 350
Spartan 6 Family XC6SLX4 -4 ISE 14.4 Y 75 173 0 0 0 0 270
SPARTAN3E Family XC3S100E -5 ISE 14.4 Y 190 264 0 0 0 0 162
KINTEX-U Family XCKU035 -3 Vivado 2017.1 Y 42 222 0 0 0 0 520
VIRTEX-U Family XCVU065 -3 Vivado 2015.1 Y 44 246 0 0 0 0 500

IP 质量指标

综合信息

数据创建日期 Jan 10, 2022
当前 IP 修订号 4.01
当前修订日期已发布 Jan 04, 2011
第一版发布日期 Mar 04, 2000

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 10
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL, Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 Verilog, VHDL
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? N
是否提供软件驱动程序? Y
驱动程序的操作系统支持 no

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 none
所支持的综合软件工具及版本 Xilinx XST; Synplicity Synplify; Mentor Precision; Other
是否执行静态时序分析? Y
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Executable and documented plan
测试方法 Both
断言 N
收集的覆盖指标 Code, Functional, Assertion
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 FPGA
已通过的行业标准合规测试 N
测试日期 Jun 20, 2000
是否提供测试结果? Y