logiWIN Versatile Video Input Controller

  • 产品编号: logiWIN
  • 供应商: Xylon d.o.o.
  • Premier Partner


The logiWIN IP core accepts a streaming video input, decodes it and converts into the RGB format. The input video can be real-time scaled, de-interlaced, cropped and positioned on the video display. Captured video can be processed by various IP cores and displayed by a graphics controller IP, i.e. the logiCVC-ML Compact Multilayer Video Controller LCD display controller IP core from Xylon. The logiWIN integrates high-quality anti-aliasing algorithm that guarantees high picture quality without visible artifacts. The core is fully embedded into Xilinx Vivado and ISE Design Suites, and its usage does not require skills beyond general Xilinx tools knowledge. Parametrizable VHDL design allows tuning of slice consumption and features set through implementation tools GUI interface. Instantiations of multiple logiWIN IPs enable processing of multiple video inputs within a single Xilinx FPGA device. To enable an easy IP evaluation, Xylon offers a number of free reference designs for the most popular Zynq-7000 SoC based development boards.


  • Double or triple buffering for video flicker prevention
  • Provides Bob ad Weave de-interlacing algorithms
  • Maximum input and output resolutions are 2048x2048
  • Supports Pixel Alpha blending
  • Supported busses: AMBA AXI4 and Xylon XMB
  • Video input cropping and smooth image positioning
  • Image color enhancements: brightness, contrast, hue, saturation
  • Output video formats: RGB ad YCbCr
  • Input video formats: RGB, ITU656 (PAL/NTSC), ITU1120, YUV4:2:2
  • Real-time video scale-up and scale down




系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado ML 2021.1 Y 0 2393 6 8 0 0 240
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2019.1 0 2993 6 8 0 0 200
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 Y 732 1625 4 11 0 0 170
Spartan 6 Family XC6SLX75 -3 ISE 14.4 Y 427 834 3 6 0 0 200
VIRTEX6LXT Family XC6VLX75T -3 ISE 14.4 Y 446 823 3 6 0 0 280

IP 质量指标


数据创建日期 Feb 16, 2022
当前 IP 修订号 5.2.1
当前修订日期已发布 Feb 06, 2020
第一版发布日期 Mar 12, 2009

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 55
可否提供参考? N


可供购买的 IP 格式 Bitstream, Netlist, Source Code
源代码格式 VHDL
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? Y
评估板所用的 FPGA Spartan-6
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference, Instantiation
所支持的综合软件工具及版本 Xilinx XST
是否执行静态时序分析? Y
AXI 接口 AXI4, AXI4-Lite
是否包含 IP-XACT 元数据? N


是否有可用的文档验证计划? Yes, document only plan
测试方法 Directed Testing
断言 N
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 N
所支持的仿真器 Mentor ModelSIM


在 FPGA 上进行验证 Y
所使用的硬件验证平台 ZC702
已通过的行业标准合规测试 N