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JPEG 2000 multi-channel HD/DCI decoder

  • 产品编号: BA109
  • 供应商: Silex Inside SA
  • 联盟计划等级: Certified


The BA109 IP core is a JPEG 2000 hardware decoder dedicated to DCI (Digital Cinema Initiatives) and HD video applications. It decodes streams compliant with the ISO/IEC 15444-1 specification (JPEG 2000). It is compliant with the DCI recommendation for video coding. It performs JPEG 2000 decoding on un-tiled large color frames with 4:4:4, 4:2:2 or 4:2:0 sub-sampling.

The core performs the complete video decompression operations of the normalized decoding process: stream parsing and header decoding, entropy decoding, inverse quantization, inverse discrete wavelet transform (IDWT) and inverse color transform (ICT/RCT). It supports a JPEG 2000 j2c file at its input interface and generates decoded samples at its output interface with up to 12 bits per color component.

The core is optimized for speed and is able to deal with the demanding DCI and HD processing requirements: it is able to provide a single-chip FPGA solution for all 2K@24fps, 2K@48fps, 2K3D@24fps, 4K@24fps, 4K3D@24fps, 720p30/60, 1080i and 1080p30/60 distributions.

The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography decoders.


  • Compliant with JPEG 2000 (ISO/IEC 15444-1) and DCI (Digital Cinema Initiatives) recommendation.
  • Customizable input bit rate up to 250Mbps / 500Mbps / 1+Gbps / lossless.
  • Full-frame decoding (no tiling).
  • Fully autonomous decoder with automatic parameter extraction, thus requirering minimal user intervention.
  • Fully synchronous design.
  • Multi-channel interface.
  • Pixel depth up to 12 bits per color sample (lossless mode up to 16 bits).
  • Single-chip FPGA solution for single-channel or multi-channel up to 4096x2160 (4K) resolution.
  • XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for ICT/RCT color transform.



系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A200T -1 ISE 14.4 Y 0 0 0 0 0 0 0

IP 质量指标


数据创建日期 Sep 25, 2017
当前 IP 修订号 1.6
当前修订日期已发布 Aug 12, 2010
第一版发布日期 Dec 22, 2006

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 10
可否提供参考? N


可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? Y
评估板所用的 FPGA Virtex-5
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Windows XP, Windows Vista, Linux


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference, Instantiation
定制 FPGA 优化技术 Memories & DSP
所支持的综合软件工具及版本 Synplicity Synplify / All; Xilinx XST / All
是否执行静态时序分析? Y
是否包含 IP-XACT 元数据? N


是否有可用的文档验证计划? Yes, executable and documented
测试方法 Directed Testing
断言 Y
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Mentor ModelSIM / All; Other / All


在 FPGA 上进行验证 Y
所使用的硬件验证平台 Virtex-5, Virtex-6
已通过的行业标准合规测试 N/A
特定的合规测试 N/A
是否提供测试结果? N