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logiCVC-ML Compact Multilayer Video Controller

产品描述

The logiCVC-ML IP core is an advanced display graphics controller that enables an easy video and graphics integration into embedded systems with the Xilinx SoC, MPSoC and FPGA devices. It can be used as a standalone graphics IP core, or as a part of larger graphics systems along with other Xylon logicBRICKS IP cores. The logiCVC-ML is a real plug-and-play IP core, prepared for Xilinx Vivado Design Suite, and designers familiar with these tools can immediately start designing. The IP's size and features can be easily adjusted through IP drag and drop tools GUI interface. The logiCVC-ML comes ready-to-use and with the rich set of deliverables including SW driver and documentation. Currently Xylon offers software drivers for use with Linux®, Android(TM) and Microsoft® Windows® Embedded Compact operating systems. Free Xylon reference design for popular Zynq-7000 SoC based development kits enable quick and risk-free evaluation.


主要特性与优势

  • Supported output formats: Parallel RGB, Parallel YUV, PAL/NTSC, LVDS, Camera link, DVI
  • Configurable AMBA AXI4, AXI4-Lite and AXI4-Stream interfaces
  • Pixel, Layer, or Color Lookup Table (CLUT) alpha blending
  • Configurable layer's size, position and offset
  • Supports up to 5 layers
  • Up to 8192x8192 display resolutions (including 4K2K@60)
  • Supports LCD TFT and CRT displays
  • Software drivers for Linux, Android and Microsoft Windows Embedded Compact
  • Free reference designs: logiREF-ZGPU-ZC702, logiREF-ZGPU-ZC706, logiREF-ZGPU-ZED

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado 2018.2 Y 283 542 1 0 0 0 333
KINTEX-7 Family XC7K355T -2 Vivado 2018.2 Y 285 477 1 0 0 0 200
ARTIX-7 Family XC7A100T -2 Vivado 2018.2 Y 283 443 1 0 0 0 130
Zynq-7000 Family XC7Z020 -1 Vivado 2016.2 Y 281 489 1 0 0 0 220
Spartan 6 Family XC6SLX25 -3 Vivado 2014.4 Y 411 808 2 0 0 0 206
VIRTEX6LXT Family XC6VLX75T -1 Vivado 2014.4 Y 394 681 767 0 0 0 200

IP 质量指标

综合信息

数据创建日期 Jan 21, 2019
当前 IP 修订号 5.4
当前修订日期已发布 Jan 17, 2019
第一版发布日期 Apr 09, 2010

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 70
可否提供参考? Y

交付内容

可供购买的 IP 格式 Bitstream, Netlist, Source Code
源代码格式 VHDL
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? Y
评估板所用的 FPGA Zynq UltraScale+ MPSoC
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux, WEC7, Android

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference, Instantiation
所支持的综合软件工具及版本 Xilinx XST
是否执行静态时序分析? Y
AXI 接口 AXI4, AXI4-Lite
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Directed Testing
断言 Y
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 N
所支持的仿真器 Mentor ModelSIM

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 ZC702, ZU102
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