SD Card / eMMC Host IP

产品描述

The SD 3.0/SDIO 3.0/eMMC 5.1 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies: SD 3.0 SDIO 3.0 eMMC 5.1 The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 3.0 / eMMC5.1 Host IP. eMMC 5.1 is backward compatible to the previous versions.


主要特性与优势

  • Compliant with eMMC Specification Version 5.1
  • AMBA AXI Specification Version 3.00 (Standard)
  • AMBA AHB Specification Version 2.00 (Optional)
  • OCP specification Version 2.2 (Optional)
  • Host clock rate variable between 0 and 200 MHz
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface
  • Supports eMMC5.1 Security Protocol Commands
  • Supports 32-bit and 64-bit system bus
  • Configurable FIFO size to support different block sizes
  • Supports Interrupts and wake up functionality
  • Supports Internal Clock divider for various card operational modes
  • HS400 high speed interface timing mode of up to 400 MB/s data rate
  • Field firmware update
  • eMMC device health report
  • eMMC production state awareness
  • Secure removal types
  • Backward compatible to 1-bit, 4-bit and 8-bit modes
  • Supports Primary & alternate boot modes
  • Supports Packed commands, Data Tags, Discard & Sanitize features
  • Supports 4KB block support
  • Supports Tuning for HS200 mode
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Password protection of Cards
  • SD Host Controller Spec v3.0* (SDXC)
  • SDIO Spec v3.0
  • SD Memory Spec v3.01
  • eSD Memory Spec v2.1

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -1 Vivado 2018.2 N 4692 6227 1 0 0 0 200

IP 质量指标

综合信息

数据创建日期 Nov 12, 2020
当前 IP 修订号 1P12
当前修订日期已发布 Mar 11, 2016
第一版发布日期 Oct 12, 2014

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 10
可否提供参考? Y

交付内容

可供购买的 IP 格式 Source Code
源代码格式 Verilog
是否包含高级模型? Y
模型格式 Other
提供集成测试台 Y
集成测试台格式 OVM System Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? UCF & SDF
商业评估板是否可用? N
评估板所用的 FPGA Virtex UltraScale+
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Fedora, Ubuntu

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 UltraFast Design Methodology
定制 FPGA 优化技术 Vivado
所支持的综合软件工具及版本 Xilinx XST
是否执行静态时序分析? Y
AXI 接口 AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Both
断言 Y
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim

硬件验证

在 FPGA 上进行验证 N
所使用的硬件验证平台 Vivado
已通过的行业标准合规测试 N
是否提供测试结果? N