Xilinx HMC Controller

Overview

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Product Description

The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect with external HMC (Hybrid Memory Cube) devices.  The core provides either Xilinx HMC Transaction Layer or AXI4-MM interface


Key Features and Benefits

  • Fully compliant with Hybrid Memory Cube Specification Revision 1.x
  • Support 10 Gb/s, 12.5 Gb/s, 15 Gb/s SerDes I/O interface
  • Support either GTH or GTY transceiver use
  • Support both HMC link modes
    • Half-width link (8-lane) supported
    • Full-width link (16-lane) supported
  • Up to 240 Gb/s full-duplex bandwidth
  • Two interface modes
    • HMC core mode provides Xilinx HMC Transaction Layer with host controller only instantiation. Allows you todevelop your user layer to interface between the user logic and controller IP
    • HMC user mode provides standard AXI4-MM interface with Xilinx HMC user layer logic
  • AXI4-Lite slave interface for configuration access
  • Configurable internal bus width (2~12 flit)
  • Support dynamic lane detection and reversal
  • Support user defined lane-to-lane mappings
  • Support dynamic lane polarity inversion
  • Optional user ID reorder logic
  • Optional data channel alignment bypass for area optimization

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