Resource Utilization for MicroBlaze Debug Module (MDM) v3.2

Vivado Design Suite Release 2016.4

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

  • Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
  • The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
  • The frequencies used for clock inputs are stated for each test case.
  • LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
  • Default Vivado Design Suite 2016.4 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix 7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7a200t fbg676 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 92 111 40 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 44 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 100 115 40 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 242 169 47 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 164 174 86 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 203 202 60 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 317 380 132 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 380 350 195 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 189 201 87 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 347 165 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 392 265 144 0 0 0 PRODUCTION 1.16 2016-11-09
xc7a200t fbg676 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1358 896 283 0 0 0 PRODUCTION 1.16 2016-11-09

Kintex 7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 92 111 43 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 44 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 100 115 37 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 242 169 50 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 164 174 85 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 200 202 60 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 317 380 134 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 382 350 188 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 189 201 89 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 347 164 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 392 265 144 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t ffg900 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1362 896 276 0 0 0 PRODUCTION 1.12 2014-09-11

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 87 111 36 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 90 113 39 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 96 115 35 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 237 169 52 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 159 174 80 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 195 202 63 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 314 380 123 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 377 350 172 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 185 201 88 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 345 347 173 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 387 265 140 0 0 0 PRODUCTION 1.23 12-12-2016
xcku040 ffva1156 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1357 896 281 0 0 0 PRODUCTION 1.23 12-12-2016

Virtex 7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1761 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 92 111 47 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 42 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 100 115 39 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 242 169 47 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 164 174 87 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 201 202 58 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 319 380 137 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 381 350 191 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 189 201 91 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 347 163 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 392 265 148 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1361 896 286 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 87 111 36 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 90 113 40 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 97 115 38 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 238 169 52 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 158 174 79 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 198 202 60 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 312 380 129 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 374 350 180 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 184 201 90 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 345 347 164 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 385 265 144 0 0 0 PRODUCTION 1.25 12-12-2016
xcvu065 ffvc1517 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1356 896 276 0 0 0 PRODUCTION 1.25 12-12-2016

COPYRIGHT

Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.