Documentation
Explore all Zynq UltraScale+ MPSoC white papers, data sheets, documentation and more.
Heterogeneous Multiprocessing Platform for Broad Range of Embedded Applications
With typical lifespans extending well past 15 years, you can depend on AMD devices for the life of your design—extending AMD 7 Series FPGAs and adaptive SoCs through 2040 and AMD UltraScale+™ FPGAs and adaptive SoCs through 2045.
AMD Zynq™ UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Built on a common real-time processor and programmable logic equipped platform, three distinct variants include dual application processor (CG) devices, quad application processor and GPU (EG) devices, and video codec (EV) devices, creating unlimited possibilities for applications such as 5G Wireless, Next-generation ADAS, and Industrial Internet-of-Things.
Multiple processing engines enable the optimization of functions across an entire application, with programmable hardware providing further performance and safety handling.
InFO devices are 60% smaller, 70% thinner, with better thermal dissipation and higher signal integrity, all without sacrificing the processing power of the Zynq UltraScale+ MPSoC.
Zynq UltraScale+ EV devices include a video codec capable of low latency simultaneous encode and decode up to 4K resolution at 60 frames per second.
Free scalable computation engine optimized for convolutional neural networks, supporting common frameworks, leveraging large repositories of pre-trained AI models.
Vast distributed on-chip memory: LUTRAM, Block RAM, UltraRAM, L3 Cache, minimizing memory access latency and allowing accelerators or co-processors to achieve maximum performance. Localized memory also allows full function isolation necessary for safety critical applications.
Flexible architecture capable of reducing power consumption by eliminating static power of unused blocks, for up to 30% less1 static power consumption. Operate as low as 180 nW in full Deep Sleep mode for maximum power savings when idle.
1. ZUS-007. See “Managing Power and Performance with the Zynq UltraScale+ MPSOC” whitepaper, page 7.
Highlight the difference at a glance.
ZU1CG | ZU2CG | ZU3CG | ZU3TCG | ZU4CG | ZU5CG | ZU6CG | ZU7CG | ZU9CG | |
---|---|---|---|---|---|---|---|---|---|
Application Processing Unit | Dual-core Arm Cortex-A53 MPCore™ up to 1.3 GHz | ||||||||
Real-Time Processing Unit | Dual-core Arm Cortex-R5F MPCore up to 533 MHz | ||||||||
Dynamic Memory Interface | DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 | ||||||||
High-Speed Peripherals | PCIe® Gen2, USB3.0, SATA 3.1, DisplayPort™, Gigabit Ethernet |
ZU1CG | ZU2CG | ZU3CG | ZU3TCG | ZU4CG | ZU5CG | ZU6CG | ZU7CG | ZU9CG | |
---|---|---|---|---|---|---|---|---|---|
System Logic Cells (K) | 81 | 103 | 154 | 157 | 192 | 256 | 469 | 504 | 600 |
Total RAM (Mb)* | 4.8 | 6.5 | 9.4 | 21.2 | 20.6 | 26.6 | 32 | 44.2 | 40.9 |
DSP Slices | 216 | 240 | 360 | 576 | 728 | 1,248 | 1,973 | 1,728 | 2,520 |
16.3 Gb/s Transceiver Count | - | - | - | 8 | 16 |
16 | 24 |
24 | 24 |
PCI Express | - | - | - | 1x Gen3x8 | 2x Gen3x8 or 1x Gen3x16 |
2x Gen3x8 or 1x Gen3x16 |
- | 1x Gen3x16 and 1x Gen3x8 |
- |
Maximum I/O Pins | 180 | 252 | 252 | 124 | 252 | 252 | 328 | 464 | 328 |
* Total RAM= Maximum Distributed RAM + Total Block RAM + UltraRAM
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1. ZUS-007. See “Managing Power and Performance with the Zynq UltraScale+ MP SOC” whitepaper, page 7.