General Description: As designs are becoming extremely large, the teams designing them are also becoming larger. Sometimes, different portions of the team synthesize their designs separately; designs may also be synthesized under different projects. Because of this, the synthesis tool may inadvertently assign the same BLKNM to primitives in different netlists.
Because the same BLKNM might appear on more primitives than a slice or CLB can accommodate, this problem can cause MAP to issue errors such as:
ERROR:Pack:679 - Unable to obey design constraints (BLKNM = <block_name>)
This is not a bug.
The user can go into the different netlists and change the BLKNM value to a different value. Remember to change this for all the same values in the same netlist.
You can also change the BLKNM attribute in the EDIF netlist to an HBLKNM attribute. To do this, do a "Find/Replace - BLKNM->HBLKNM" for all of the BLKNMs in the netlist. HBLKNM will append the design hierarchical name on the component, making the original block name unique.
This problem has been fixed in FPGA Express version 3.5.
You can change all the BLKNM attributes to HBLKNM attributes. This will cause the attribute to see only itself in its own hierarchy. Thus, two netlists which may have equal HBLKNM values for some of the primitives will have no effect on each other.
The different designers can synthesize all the code under one project.
A variation of this error message has been seen when unconnected I/Os existed in the user's HDL code.