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  3. AR# 10070: 3.x FPGA Express - How do I instantiate and initialize LUT primitives in HDL for Virtex?

AR# 10070

3.x FPGA Express - How do I instantiate and initialize LUT primitives in HDL for Virtex?

描述

Keywords: Express, Synopsys, LUT, instantiate, initialize, VHDL, Verilog, HDL, Virtex

Urgency: Standard

General Description:
How do I instantiate and initialize LUT primitives in HDL for Virtex using Synopsys FPGA Express?

解决方案

1

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specify its function. Please refer to the Libraries Guide for more information on LUTs:
http://support.xilinx.com/support/library.htm

(NOTE: Works with FPGA Express 3.4 or newer)


VHDL Example

library IEEE;
use IEEE.std_logic_1164.all;

entity LUTs is
port ( LUT0_IN, LUT1_IN, LUT2_IN, LUT3_IN : in STD_LOGIC;
LUT_OUT : out STD_LOGIC
);
end LUTs;

architecture XILINX of LUTs is

component LUT4
port(
O : out STD_LOGIC;
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC
);
end component;

attribute INIT: string;
attribute INIT of LUT_EXAMPLE : label is "8000";

begin
-- LUT4 used as a 4-input AND gate
LUT_EXAMPLE: LUT4 port map(
O => LUT_OUT,
I0 => LUT0_IN,
I1 => LUT1_IN,
I2 => LUT2_IN,
I3 => LUT3_IN
);

end XILINX;

2

Verilog Example

// LUT
// Four input AND gate

module LUT4_EXAMPLE (O, I0, I1, I2, I3);
input I0, I1, I2, I3;
output O;

LUT4 U1 (.O(O), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
//synopsys attribute INIT "8000"

endmodule
AR# 10070
日期 08/11/2003
状态 Archive
Type 综合文章