AR# 10075: 7.1i XST - "ERROR:Xst:899 - "file_name", line #: The logic for "net_name" does not match a known FF or Latch template"
AR# 10075
7.1i XST - "ERROR:Xst:899 - "file_name", line #: The logic for "net_name" does not match a known FF or Latch template"
描述
General Description:
What type of clock statements does XST support?
XST does not support the use of a complex condition check inside an always block in Verilog. For example, the following code results in the error below:
always @( negedge input1 or negedge input2 or posedge clock )
begin
if ( ~input1 | ~input2 )
begin
output1 <= 1'b1;
output2 <= 1'b0;
end
else
begin
output1 <= input1;
output2 <= input2 & input1;
end
end
"ERROR:Xst:899 - "file_name", line #: The logic for "net_name" does not match a known FF or Latch template."
解决方案
To avoid this error, perform the combinatorial logic outside the always block to remove the complex clock statement from the sensitivity list, and then use that intermediate signal in the sensitivity list of the always block, as follows:
assign temp = ~input1 | ~input2;
always @( posedge temp or posedge clock )
begin
if ( temp )
begin
output1 <= 1'b1;
output2 <= 1'b0;
end
else
begin
output1 <= input1;
output2 <= input2 & input1;
end
end
When you infer hardware from HDL, it is important to keep the type of hardware you want in mind. The XST User Guide contains basic templates for the various types of FPGA/CPLD hardware that can be inferred with HDL code:
If your HDL code is modeled after the templates provided, you should be able to infer the desired hardware.
Another situation that causes this error (which is unrelated to the first example) is when the reset function in the always block has no effect on the register that will be inferred:
module misc(clk,rst,in1,out1);
input clk,rst,in1;
output[1:0] out1;
reg[1:0] out1;
always @(posedge clk or posedge rst)
begin
if (rst)
out1[1] = in1;
else
out1 = {in1,in1};
end
endmodule
change to:
module misc(clk,rst,in1,out1);
input clk,rst,in1;
output[1:0] out1;
reg[1:0] out1;
always @(posedge clk or posedge rst)
begin
if (rst)
out1[1] = 0;
else
out1 = {in1,in1};
end
endmodule
The error message also appears when a dual-edge triggered FF is inferred in any device other than a CoolRunner-II. The CoolRunner-II is the only Xilinx device that contains dual-edge triggered FFs: