UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1011

PPR issues error 9025 on 5k design; FPLAN finds no errors

Description

When PPR issues this error in a 5k design, typically you will see some
messages like this:

*** PPR: ERROR 9025:
The symbols placed in this block do not represent a legal block
configuration. Check the logic shown below against the requirements of
placement constraints, BLKNM parameters, and X and P signal
parameters.
Function generator Name = $FG_VBR8/$1I795/$1I321/D
Type = 4-input
Output Signal = VBR8/$1I795/$1I321/D
Cstfile LOC(s) = CLB_R17C14.LC0
Flip-flop = VBR8/$1I795/$1I321/$1I30
Type = DFF
Output Signal = VBR8/$1I795/SRLATCHA
Cstfile LOC(s) = CLB_R17C14.LC0

解决方案

While it appears to be complaining about a placement problem; the issue is
actually a problem with the routing resources available to reach both the
TBUF.I and the DFF.D pins from outside the clb. There is one internal routing
"bottleneck point", called the DI node, through which external inputs can
reach either the TBUF.I or DFF.D pin. If both are being driven by separate
signals, the only hope is to sneak one of the signals ("feed-in" or "route-in")
through the slice's (slice = 1/4 of a 5k clb) function generator. But this is
impossible if the function generator is occupied.

This occurs from a floorplan that was over-packed by the designer, while
the floorplan tool claims that "The design passes all basic placement
checks!" To solve this problem, the design will need to be re-floorplanned
for the resources that PPR is complaining about.
AR# 1011
创建日期 08/31/2007
Last Updated 05/24/1999
状态 Archive
Type ??????