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AR# 10130

6.1 System Generator for DSP - Can I generate Verilog HDL code?

描述

Keywords: MathWorks, MATLAB, Simulink, SysGen, token

When I use the System Generator token to generate my Xilinx design, I see only VHDL code being generated. Can I generate Verilog code?

解决方案

Starting with System Generator for DSP 6.3, you can now generate Verilog Code.

The System Generator for DSP Users Guide lists the limitations of Verilog Netlisting.
AR# 10130
日期 07/18/2007
状态 Archive
Type 综合文章
的页面